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參數(shù)資料
| 型號(hào)： | OZ6912 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single-Slot ACPI CardBus Controller |
| 中文描述： | 單槽ACPI的CardBus控制器 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大小： | 140K |
| 代理商： | OZ6912 |
OZ6912
OZ6912-SF-1.5
Page 5
Pin List
Bold Text
= Normal Default Pin Name
PCI Bus Interface Pins
Pin Number
LQFP
3-5, 7-11, 15-
17, 19, 23-26,
38-41, 43, 45-
47, 49, 51-57
Pin Name
Description
BGA
Input
Type
Power
Rail
PCI_Vcc
Drive
AD[31:0]
PCI Bus Address/Data:
These pins connect to
PCI bus signals AD[31:0]. A Bus transaction
consists of an address phase followed by one or
more data phases.
C2, C1, D4, D2,
D1, E4, E3, E2,
F2, F1, G2, G3,
H3, H4, J1, J2,
N2, M3, N3,
K4, M4, K5, L5,
M5, K6, M6,
N6, M7, N7, L7,
K7, N8
E1, J3, N1, N5
TTL
I/O
PCI
Spec
C/BE[3:0]#
PCI Bus Command / Byte Enable:
The
command signaling and byte enables are
multiplexed on the same pins. During the address
phase of a transaction, C/BE[3:0]# are interpreted
as the bus commands. During the data phase,
C/BE[3:0]# are interpreted as byte enables. The
byte enables are to be valid for the entirety of
each data phase, and they indicate which bytes in
the 32-bit data path are to carry meaningful data
for the current data phase.
Cycle Frame:
This signal indicates to the OZ6912
that a bus transaction is beginning. While
FRAME# is asserted, data transfers continue.
When FRAME# is de-asserted, the transaction is
in its final phase.
Initiator Ready:
This signal indicates the initiating
agent
’
s ability to complete the current data phase
of the transaction. IRDY# is used in conjunction
with TRDY#.
Target Ready:
This signal indicates target
Agent's the OZ6912
’
s ability to complete the
current data phase of the transaction. TRDY# is
used in conjunction with IRDY#.
Stop:
This signal indicates the current target is
requesting the master to stop the current
transaction.
Initialization Device Select:
This input is used as
chip select during configuration read and write
transactions. This is a point-to-point signal.
IDSEL can be used as a chip select during
configuration read and write transactions.
Device Select:
This signal is driven active LOW
when the PCI address is recognized as
supported, thereby acting as the target for the
current PCI cycle. The Target must respond
before timeout occurs or the cycle will terminate.
Parity Error:
The output is driven active LOW
when a data parity error is detected during a write
phase.
System Error:
This output is driven active LOW
to indicate an address parity error.
12, 27, 37, 48
TTL
I/O
PCI_Vcc
PCI
Spec
FRAME#
28
J4
TTL
I/O
PCI_Vcc
PCI
Spec
IRDY#
29
K1
TTL
I/O
PCI_Vcc
PCI
Spec
TRDY#
31
K3
TTL
I/O
PCI_Vcc
PCI
Spec
STOP#
33
L2
TTL
I/O
PCI_Vcc
PCI
Spec
IDSEL
13
F4
TTL
I
PCI_Vcc
PCI
Spec
DEVSEL#
32
L1
TTL
I/O
PCI_Vcc
PCI
Spec
PERR#
34
L3
-
TO
PCI_Vcc
PCI
Spec
SERR#
35
M1
-
TO
PCI_Vcc
PCI
Spec
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OZ6912B | Single-Slot ACPI CardBus Controller |
| OZ6912T | Single-Slot ACPI CardBus Controller |
| OZ6933 | ACPI CardBus Controller |
| OZ6933B | ACPI CardBus Controller |
| OZ6933T | ACPI CardBus Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OZ6912B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Slot ACPI CardBus Controller |
| OZ6912T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Slot ACPI CardBus Controller |
| OZ6933 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ACPI CardBus Controller |
| OZ6933B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ACPI CardBus Controller |
| OZ6933T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ACPI CardBus Controller |
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