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| 型號(hào)： | OR3T125-4BC432I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 784 CLBS, 92000 GATES, 80 MHz, PBGA432 |
| 封裝： | BGA-432 |
| 文件頁(yè)數(shù)： | 158/210頁(yè) |
| 文件大?。?/td> | 2138K |
| 代理商： | OR3T125-4BC432I |
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Lucent Technologies Inc.
51
Preliminary Data Sheet, Rev. 1
September 1998
ORCA Series 3 FPGAs
Special Function Blocks
Special function blocks in the Series 3 provide extra
capabilities beyond general FPGA operation. These
blocks reside in the corners and MIDs (middle inter-
quad areas) of the FPGA array.
Single Function Blocks
Most of the special function blocks perform a specific
dedicated function. These functions are data/configura-
tion readback control, global 3-state control (TS_ALL),
internal oscillator generation, global set/reset (GSRN),
and start-up logic.
Readback Logic
The readback logic is located in the upper right corner
of the FPGA and can be enabled via a bit stream
option or by instantiation of a library readback compo-
nent.
Readback is used to read back the configuration data
and, optionally, the state of the PFU outputs. A read-
back operation can be done while the FPGA is in nor-
mal system operation. The readback operation cannot
be daisy-chained. To use readback, the user selects
options in the bit stream generator in the
ORCA
Foundry Development System.
Table 12 provides readback options selected in the bit
stream generator tool. The table provides the number
of times that the configuration data can be read back.
This is intended primarily to give the user control over
the security of the FPGA’s configuration program. The
user can prohibit readback (0), allow a single readback
(1), or allow unrestricted readback (U).
Readback can be performed via the Series 3 micropro-
cessor interface (MPI) or by using dedicated FPGA
readback controls. If the MPI is enabled, readback via
the dedicated FPGA readback logic is disabled. Read-
back using the MPI is discussed in the Microprocessor
Interface (MPI) section.
The pins used for dedicated readback are readback
data (RD_DATA), read configuration (RD_CFG), and
configuration clock (CCLK). A readback operation is
initiated by a high-to-low transition on RD_CFG. The
RD_CFG
input must remain low during the readback
operation. The readback operation can be restarted at
frame 0 by driving the RD_CFG pin high, applying at
least two rising edges of CCLK, and then driving
RD_CFG
low again. One bit of data is shifted out on
RD_DATA at the rising edge of CCLK. The first start bit
of the readback frame is transmitted out several cycles
after the first rising edge of CCLK after RD_CFG is input
low (see the Readback Timing Characteristics table in
the Timing Characteristics section). To be certain of the
start of the readback frame, the data can be monitored
for the 01 frame start bit pair.
Readback can be initiated at an address other than
frame 0 via the new microprocessor interface (MPI)
control registers (see the Microprocessor Interface
(MPI) section for more information). In all cases, read-
back is performed at sequential addresses from the
start address.
It should be noted that the RD_DATA output pin is also
used as the dedicated boundary-scan output pin, TDO.
If this pin is being used as TDO, the RD_DATA output
from readback can be routed internally to any other pin
desired. The RD_CFG input pin is also used to control
the global 3-state (TS_ALL) function. Before and dur-
ing configuration, the TS_ALL signal is always driven
by the RD_CFG input and readback is disabled. After
configuration, the selection as to whether this input
drives the readback or global 3-state function is deter-
mined by a set of bit stream options. If used as the
RD_CFG
input for readback, the internal TS_ALL input
can be routed internally to be driven by any input pin.
Table 12. Readback Options
Option
Function
0
Prohibit Readback
1
Allow One Readback Only
U
Allow Unrestricted Number of Readbacks
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR3T80-4BC432I | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA432 |
| OR3C80-4BC600I | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA600 |
| OR3C80-5BC600I | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA600 |
| OR3T125-4BC600I | FPGA, 784 CLBS, 92000 GATES, 80 MHz, PBGA600 |
| OR3T80-4BC600I | FPGA, 484 CLBS, 58000 GATES, 80 MHz, PBGA600 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3T125-4BC600I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T125-4PS208I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T125-4PS240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T125-5BA352 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T125-5BA352I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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