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8
OPA654
The OPA654 may be operated at reduced power supply
voltage, thus reducing internal power dissipation. This can
eliminate the need for heat sinking in some applications.
OUTPUT CURRENT LIMIT
Output current is limited by internal circuitry to approxi-
mately 325mA at 25
°
C. The limit current decreases with
increasing junction temperature as shown in the typical
curves. The combination of current limit and thermal limit
protects the device from short circuits to ground.
INPUT BIAS CURRENT
The OPA654 is fabricated with Burr-Brown’s dielectrically
isolated
Difet
process, giving it very low input bias current.
Like other FET amplifiers, input bias current doubles for
every 10
°
C increase in junction temperature. This increase
can be minimized by providing a heat sink and, if possible,
operating with reduced power supply voltage to minimize
power dissipation.
FIGURE 4. G = +1 Amplifier with Alternative Compensa-
tion.
G = +1 LARGE-SIGNAL RESPONSE, R
L
=100
FPO
Figure 3 also demonstrates a compensation technique using
an additional network, R
-C
. This allows use of a smaller
value for C
, producing a corresponding increase in slew
rate. It reduces the high frequency loop gain by placing the
op amp in a higher noise gain at high frequency. This
technique improves large-signal response at the sacrifice of
small-signal behavior. Settling time is increased and high
frequency noise performance will be somewhat degraded.
Figure 4 shows an alternative compensation network for
unity gain. This technique provides a small amount of
positive feedback, reducing the net negative feedback factor.
Large signal response and load driving capability is im-
proved with this approach.
The compensation for a given application can be evaluated
by observing amplifier pulse response. Both small-signal
and large-signal response should be checked to assure that
both are acceptable. Large overshoot or many cycles of
ringing in the small-signal response is a sign of instability
and the circuit may require further optimization. Good
practice dictates a somewhat conservative approach to allow
for device-to-device variation.
POWER DISSIPATION
Many applications do not require an external heat sink.
However, with high ambient temperature or heavy load
conditions, a heat sink may be required. The heat sink should
be electrically connected to ground—see “Connections to
Case”. Operate within the power derating curve (Maximum
Power Dissipation vs Temperature) shown in the typical
performance curve section.
Exceeding the maximum die temperature of 165
°
C may
activate the internal thermal limit circuitry, disabling the
output stage. This thermal limit is set for a junction tempera-
ture of approximately 185
°
C.
R
S
= 5
to 50
(see text)
FIGURE 3. High Slew Rate Compensation Circuit.
C
1000pF
C
3pF
1
R
2
R
3
R
100
L
Comp
2k
3
680
R
1
2k
I
V
R
S
OUT
V
G = –1
2pF
OPA654
1
5
6
3
50
R
C
7pF
1
R
100
L
Comp
1000pF
470
470
TERM
10
V
OUT
G = +1
OPA654
1
5
6
3
V
O
+10
–10
0