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參數(shù)資料
| 型號： | OPA628AU |
| 英文描述： | Low Distortion Wideband OPERATIONAL AMPLIFIER |
| 中文描述： | 低失真寬帶運算放大器 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大小： | 172K |
| 代理商： | OPA628AU |
10
OPA628
OPA628
C
L
R
L
R
S
(R typically 5 to 25 )
NOISE FIGURE vs SOURCE RESISTANCE
25
20
15
10
5
0
10
100
1k
10k
100k
N
Source Resistance (
)
NF
dB
= 10log 1 + e
n2
+ (i
n
R
S
)
2
4kTRS
SETTLING TIME
Settling time is defined as the total time required, from the
input signal step, for the output to settle to within the
specified error band around the final value. This error band
is expressed as a percentage of the value of the output
transition, a 2V step. Thus, settling time to 0.01% requires an
error band of
±
200
μ
V centered around the final value of 2V.
Settling time, specified in an inverting gain of one, is only
64ns to 0.01% for a 2V step. Settling time increases with
closed-loop gain and output voltage change as described in
the Typical Performance Curves. Preserving settling time
requires critical attention to the details as mentioned under
“Printed Circuit Board Guidelines.” The amplifier also re-
covers quickly from input overloads. Overload recovery
time to linear operation from a 50% overload is typically
only 60ns. Settling time measurements for the OPA628 were
performed in the circuit configuration of Figure 5. A sam-
pling oscilloscope was used with signal averaging.
CAPACITIVE LOADS
Capacitive loads will decrease the OPA628’s phase margin
which may cause high frequency peaking or oscillations.
Capacitive loads greater than 20pF should be buffered by
connecting a small resistance, usually 5
to 25
, in series
with the output as shown in Figure 4. This is particularly
important when driving high capacitance loads such as flash
A/D converters.
FIGURE 4. Driving Capacitive Loads.
FIGURE 3. Noise Figure vs Source Resistance.
In general, capacitive loads should be minimized for opti-
mum high frequency performance. Coax lines can be driven
if the cable is properly terminated. The capacitance of coax
cable (29pF/ft for RG-58) will not load the amplifier when
the coaxial cable or transmission line is terminated in its
characteristic impedance.
COMPENSATION
The OPA628 is internally compensated and is stable in unity
gain with a phase margin of approximately 60
°
. However,
the unity gain buffer is the most demanding circuit configu-
ration for loop stability and oscillations are most likely to
occur in this gain. If possible, use the device in a noise gain
of two or greater to improve phase margin and reduce the
susceptibility to oscillation. (Note that, from a stability
standpoint, an inverting gain of –1V/V is equivalent to a
noise gain of 2V/V.) Gain and phase response for other gains
are shown in the Typical Performance Curves.
The high-frequency response of the OPA628 in a good
layout is
very flat with frequency. However, some circuit
configurations, such as those where large feedback resis-
tances are used, can produce high-frequency gain
peaking.
This peaking can be minimized by connecting a small
capacitor in parallel with the feedback resistor. This capaci-
tor compensates for the closed-loop, high frequency, transfer
function zero that results from the time constant formed by
the input capacitance of the amplifier (typically 2pF after PC
board mounting), and the input and feedback resistors. The
selected compensation capacitor may be a trimmer, a fixed
capacitor, or a planned PC board capacitance. The capaci-
tance value is strongly dependent on circuit layout and
closed-loop gain. Using small resistor values will preserve
the phase margin and avoid peaking by keeping the break
frequency of this zero sufficiently high. When high closed-
loop gains are required, a three-resistor attenuator (tee net-
work) is recommended to avoid using large value resistors
with large time constants.
THERMAL CONSIDERATIONS
The OPA628 does not require a heat sink for operation in
most environments. The use of a heat sink, however, will
reduce the internal thermal rise and will result in cooler,
more reliable operation. At extreme temperatures and under
full load conditions a heat
sink is necessary. See “Maximum
Power Dissipation” curve, Figure 6.
The internal power dissipation is given by the equation
P
D
= P
DQ
+ P
DL
, where P
DQ
is the quiescent power dissipa-
tion and P
DL
is the power dissipation in the output stage due
to the load. (For
±
V
CC
=
±
5V, P
DQ
= 10V
X
32mA =
320mW, max). For the case where the amplifier is driving a
grounded load (R
L
) with a DC voltage (V
OUT
) the maximum
valueofP
DL
occurs at
V
OUT
= V
CC
/2, and is equal to P
DL
,
max = (V
CC
)
2
/4R
L
. Note that it is the voltage across the
output transistor, and not the load, that determines the power
dissipated in the output stage.
When the output is shorted to common P
DL
= 5V
X
180mA
= 900mW. Thus, P
D
, max = 320mW + 900mW
≈
1.2W.
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