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參數(shù)資料
| 型號： | OPA3681E |
| 英文描述： | Triple Wideband, Current-Feedback OPERATIONAL AMPLIFIER With Disable |
| 中文描述： | 三寬帶，電流反饋運算放大器，禁用 |
| 文件頁數(shù)： | 19/21頁 |
| 文件大?。?/td> | 234K |
| 代理商： | OPA3681E |
19
OPA3681
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 4 shows the general form for the
output noise voltage using the terms shown in Figure 12.
Dividing this expression by the noise gain (NG = (1+R
F
/R
G
))
will give the equivalent input referred spot noise voltage at the
non-inverting input as shown in Equation 5.
Evaluating these two equations for the OPA3681 circuit and
component values shown in Figure 1 will give a total output
spot noise voltage of 8.4nV/
√
Hz and a total equivalent input
spot noise voltage of 4.2nV/
√
Hz. This total input-referred
spot noise voltage is higher than the 2.2nV/
√
Hz specifica-
tion for the op amp voltage noise alone. This reflects the
noise added to the output by the inverting current noise times
the feedback resistor. If the feedback resistor is reduced in
high gain configurations (as suggested previously), the total
input-referred voltage noise given by Equation 5 will ap-
proach just the 2.2nV/
√
Hz of the op amp itself. For example,
going to a gain of +10 using R
F
= 182
will give a total
input referred noise of 2.4nV/
√
Hz.
DC ACCURACY AND OFFSET CONTROL
A current-feedback op amp like the OPA3681 provides
exceptional bandwidth in high gains, giving fast pulse set-
tling but only moderate DC accuracy. The Specifications
Table shows an input offset voltage comparable to high-
speed, voltage-feedback amplifiers. However, the two input
bias currents are somewhat higher and are unmatched.
Whereas bias current cancellation techniques are very effec-
tive with most voltage-feedback op amps, they do not
generally reduce the output DC offset for wideband current-
feedback op amps. Since the two input bias currents are
unrelated in both magnitude and polarity, matching the
source impedance looking out of each input to reduce their
error contribution to the output is ineffective. Evaluating the
configuration of Figure 1, using worst-case +25
°
C input
offset voltage and the two input bias currents, gives a worst-
case output offset range equal to:
±
(NG V
OS(MAX)
) + (I
BN
R
S
/2 NG)
±
(I
BI
R
F
)
where NG = non-inverting signal gain
=
±
(2 5.0mV) + (55
μ
A 25
2)
±
(499
40
μ
A)
=
±
10mV + 2.75mV
±
20mV
= –27.25mV
→
+32.75mV
In normal operation, base current to Q1 is provided through
the 110k
resistor while the emitter current through the
15k
resistor sets up a voltage drop that is inadequate to
turn on the two diodes in Q1’s emitter. As V
DIS
is pulled
low, additional current is pulled through the 15k
resistor
eventually turning on these two diodes (
≈
100
μ
A). At this
point, any further current pulled out of V
DIS
goes through
those diodes holding the emitter-base voltage of Q1 at
approximately zero volts. This shuts off the collector current
out of Q1, turning the amplifier off. The supply current in
the disable mode is that only required to operate the circuit
of Figure 13. Additional circuitry ensures that turn-on time
occurs faster than turn-off time (make-before-break).
When disabled, the output and input nodes go to a high
impedance state. If the OPA3681 is operating in a gain of
+1, this will show a very high impedance (4pF || 1M
) at the
output and exceptional signal isolation. If operating at a
gain greater than +1, the total feedback network resistance
(R
F
+ R
G
) will appear as the impedance looking back into
the output, but the circuit will still show very high forward
and reverse isolation. If configured as an inverting ampli-
fier, the input and output will be connected through the
feedback network resistance (R
F
+ R
G
) giving relatively
poor input to output isolation.
One key parameter in disable operation is the output glitch
when switching in and out of the disable mode. Figure 14
shows these glitches for the circuit of Figure 1 with the input
signal set to zero volts. The glitch waveform at the output
pin is plotted along with the DIS pin voltage.
25k
110k
15k
I
Control
–V
S
+V
S
V
DIS
Q1
DISABLE OPERATION
The OPA3681 provides an optional disable feature that may
be used either to reduce system power or to implement a
simple channel multiplexing operation. If the DIS control
pin is left unconnected, the OPA3681 will operate normally.
To disable, the control pin must be asserted low. Figure 13
shows a simplified internal circuit for the disable control
feature.
FIGURE 13. Simplified Disable Control Circuit.
E
E
I
R
kTR NG
I R
kTR NG
O
NI
BN
S
F
=
+
(
)
+
(
)
+
(
)
+
2
2
2
2
4
4
Eq. 4
E
E
I
R
kTR
I R
NG
kTR
NG
N
NI
BN
S
S
F
F
=
+
(
)
+
+
+
2
2
2
4
4
Eq. 5
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| OPA3681E/250 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
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| OPA3681U | 功能描述:高速運算放大器 Triple Wideband RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 電壓增益 dB:116 dB 輸入補償電壓:0.5 mV 轉換速度:55 V/us 工作電源電壓:36 V 電源電流:7.5 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube |
| OPA3681U/2K5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| OPA3682 | 制造商:BB 制造商全稱:BB 功能描述:Triple, Wideband, Fixed Gain BUFFER AMPLIFIER With Disable |
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