
Functional Description
The NM93C13/C14 have 7 instructions as described below.
Note that the MSB of any instruction is a ‘‘1’’ and is viewed
as a start bit in the interface sequence. For the C13 and C14
the next 8 bits carry the op code and the 6-bit address for
register selection.
Read (READ):
The READ instruction outputs serial data on the DO pin.
After a READ instruction is received, the instruction and ad-
dress are decoded, followed by data transfer from the se-
lected memory register into a 16-bit serial-out shift register.
A dummy bit (logical 0) precedes the 16-bit data output
string. Output data changes are initiated by a low to high
transition of the SK clock.
Erase/Write Enable (EWEN):
When V
CC
is applied to the part, it powers up in the Erase/
Write Disable (EWDS) state. Therefore, all programming
modes must be preceded by an Erase/Write Enable
(EWEN) instruction. Once an Erase/Write Enable instruc-
tion is executed, programming remains enabled until an
Erase/Write Disable (EWDS) instruction is executed or V
CC
is removed from the part.
Erase (ERASE):
The ERASE instruction will program all bits in the specified
register to the logical ‘1’ state. CS is brought low following
the loading of the last address bit. This falling edge of the
CS pin initiates the self-timed programming cycle.
The DO pin indicates the READY/BUSY status of the chip if
CS is brought high after a minimum of 500 ns (t
CS
).
DO
e
logical ‘0’ indicates that programming is still in prog-
ress. DO
e
logical ‘1’ indicates that the register, at the
address specified in the instruction, has been erased, and
the part is ready for another instruction.
Write (WRITE):
The WRITE instruction is followed by 16 bits of data to be
written into the specified address. After the last bit of data is
put on the data-in (DI) pin, CS must be brought low before
the next rising edge of the SK clock. This falling edge of CS
initiates the self-timed programming cycle. The DO pin indi-
cates the READY/BUSY status of the chip if CS is brought
high after a minimum of 500 ns (t
CS
). DO
e
logical 0 indi-
cates that programming is still in progress. DO
e
logical 1
indicates that the register at the address specified in the
instruction has been written with the data pattern specified
in the instruction and the part is ready for another instruc-
tion.
Erase All (ERAL):
The ERAL instruction will simultaneously program all regis-
ters in the memory array and set each bit to the logical ‘1’
state. The Erase All cycle is identical to the ERASE cycle
except for the different op-code. As in the ERASE mode,
the DO pin indicates the READY/BUSY status of the chip if
CS is brought high after a minimum of 500 ns (t
CS
). The
ERASE ALL instruction is not required, see note below.
Write All (WRAL):
The WRAL instruction will simultaneously program all regis-
ters with the data pattern specified in the instruction. As in
the WRITE mode, the DO pin indicates the READY/BUSY
status of the chip if CS is brought high after a minimum of
500 ns (t
CS
).
Erase/Write Disable (EWDS):
To protect against accidental data disturb, the Erase/Write
Disable (EWDS) instruction disables all programming modes
and should follow all programming operations. Execution of
a READ instruction is independent of both the EWEN and
EWDS instructions.
Note:
The NM93C13/C14 devices do not require an ‘ERASE’ or ‘ERASE ALL’ prior to the ‘WRITE’ and ‘WRITE ALL’ instructions. The ‘ERASE’ and ‘ERASE ALL’
instructions are included to maintain compatibility with the NMOS NMC9346.
Instruction Set for the NM93C13 and NM93C14
Instruction
SB
Op Code
Address
Data
Comments
READ
1
10
A5–A0
Reads data stored in memory at specified address.
EWEN
1
00
11XXXX
Write enable must precede all programming modes.
ERASE
1
11
A5–A0
Erase selected register.
WRITE
1
01
A5–A0
D15–D0
Writes selected register.
ERAL
1
00
10XXXX
Erases all registers.
WRAL
1
00
01XXXX
D15–D0
Writes all registers.
EWDS
1
00
00XXXX
Disables all programming instructions.
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