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參數(shù)資料
| 型號： | NB4N840M |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | 3.3V 2.7Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch with CML Output and Internal Termination(帶CML輸出和內(nèi)部終端的3.3V，2.7Gb/s雙差分時鐘/數(shù)據(jù)2x2交點開關(guān)) |
| 中文描述： | 3.3 2.7Gb / s雙差分時鐘/帶CML輸出和內(nèi)部終端（帶白血病輸出和內(nèi)部終端的3.3伏，2.7Gb /數(shù)據(jù)2 × 2交叉點開關(guān)S雙差分時鐘/數(shù)據(jù)2X2的交點開關(guān)） |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 166K |
| 代理商： | NB4N840M |
NB4N840M
http://onsemi.com
3
Table 2. PIN DESCRIPTION
Pin
Name
I/O
Description
1
ENB1
LVTTL
Channel B1 Output Enable. LVTTL low input powers down B1 output stage.
2
DB1
CML Input
Channel B1 Positive Signal Input
3
DB1
CML Input
Channel B1 Negative Signal Input
4
ENB0
LVTTL
Channel B0 Output Enable. LVTTL low input powers down B0 output stage.
5
SELB0
LVTTL
Channel B0 Output Select. See Table 1.
6
DB0
CML Input
Channel B0 Positive Signal Input
7
DB0
CML Input
Channel B0 Negative Signal Input
8
SELB1
LVTTL
Channel B1 Output Select. See Table 1.
9,24
GND
Supply Ground. All GND pins must be externally connected to power supply to guarantee
proper operation.
10, 13, 16,
17, 20, 23
V
CC
Positive Supply. All V
CC
pins must be externally connected to power supply to guarantee
proper operation.
11
QB0
CML Output
Channel B0 Negative Output.
12
QB0
CML Output
Channel B0 Positive Output.
14
QB1
CML Output
Channel B1 Negative Output.
15
QB1
CML Output
Channel B1 Positive Output.
18
QA1
CML Output
Channel A1 Negative Output.
19
QA1
CML Output
Channel A1 Positive Output.
21
QA0
CML Output
Channel A0 Negative Output.
22
QA0
CML Output
Channel A0 Positive Output.
25
SELA1
LVTTL
Channel A1 Output Select, LVTTL Input. See Table 1.
26
DA0
CML Input
Channel A0 Positive Signal Input.
27
DA0
CML Input
Channel A0 Negative Signal Input.
28
SELA0
LVTTL
Channel A0 Output Select, LVTTL Input. See Table 1.
29
ENA0
LVTTL
Channel A0 Output Enable. LVTTL low input powers down A0 output stage.
30
DA1
CML Input
Channel A1 Positive Signal Input.
31
DA1
CML Input
Channel A1 Negative Signal Input.
32
ENA1
LVTTL
Channel A1 Output Enable. LVTTL low input powers down A1 output stage.
EP
GND
Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing)
must be attached to a heat
sinking conduit. The exposed pad must be soldered to the
circuit board GND for proper electrical and thermal operation.
相關(guān)PDF資料 |
PDF描述 |
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| NB6L11 | 2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1:2 CLOCK OR DATA FANOUT BUFFER / TRANSLATOR |
| NB6L11D | 2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1:2 CLOCK OR DATA FANOUT BUFFER / TRANSLATOR |
| NB6L11DR2 | 2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1:2 CLOCK OR DATA FANOUT BUFFER / TRANSLATOR |
| NB6L11DT | 2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1:2 CLOCK OR DATA FANOUT BUFFER / TRANSLATOR |
| NB6L11DTR2 | 2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1:2 CLOCK OR DATA FANOUT BUFFER / TRANSLATOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NB4N840M_07 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3.3V 3.2Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch with CML Output and Internal Termination |
| NB4N840MMNEVB | 功能描述:BOARD EVAL BBG NB4N840MMN RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:* 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| NB4N840MMNG | 功能描述:模擬和數(shù)字交叉點 IC ANA 2X2 CROSSPT SWCH CML RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube |
| NB4N840MMNR4G | 功能描述:模擬和數(shù)字交叉點 IC ANA 2X2 CROSSPT SWCH CML RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube |
| NB4N840MMNTWG | 制造商:ON Semiconductor 功能描述:DUAL DIFF 2X2 SWITCH - Tape and Reel |
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