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參數(shù)資料
| 型號(hào)： | NB3N3001 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | 3.3 V 106.25 MHz/ 212.5 MHz PureEdge Clock Generator with LVPECL Differential Output(帶LVPECL差分輸出的3.3V 106.25MHz/212.5MHz PureEdge 時(shí)鐘生成器) |
| 中文描述： | 3.3伏106.25兆赫/ 212.5兆赫的PureEdge時(shí)鐘發(fā)生器可與LVPECL差分輸出（帶的LVPECL差分輸出的3.3 106.25MHz/212.5MHz的PureEdge時(shí)鐘生成器） |
| 文件頁(yè)數(shù)： | 8/8頁(yè) |
| 文件大?。?/td> | 114K |
| 代理商： | NB3N3001 |
NB3N3001
http://onsemi.com
8
PACKAGE DIMENSIONS
TSSOP8
CASE 948S01
ISSUE B
DIM
A
B
C
D
F
G
J
J1
MIN
2.90
4.30
0.05
0.50
0.65 BSC
0.09
0.09
MAX
3.10
4.50
1.10
0.15
0.70
MIN
0.114
0.169
0.002
0.020
0.026 BSC
0.004
0.004
MAX
0.122
0.177
0.043
0.006
0.028
INCHES
MILLIMETERS
L
M
P
P1
6.40 BSC
0
0.252 BSC
0
8
2.20
3.20
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE W.
SEATING
PLANE
PIN 1
1
4
8
5
DETAIL E
B
C
D
A
G
L
2X
L/2
U
S
U
0.20 (0.008) T
S
U
M
0.10 (0.004)
V
S
T
0.076 (0.003)
T
V
W
8x REF
K
K1
0.19
0.19
0.30
0.25
0.007
0.007
0.012
0.010
S
U
0.20 (0.008) T
P1
P
DETAIL E
F
M
0.25 (0.010)
éééé
éééé
éééé
K1
K
J J1
SECTION NN
0.20
0.16
0.008
0.006
0.087
0.126
N
N
ON Semiconductor
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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LITERATURE FULFILLMENT
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Phone
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For additional information, please contact your local
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NB3N3001DTG | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 XTAL LVPECL FIBR CLK RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| NB3N3001DTR2G | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 XTAL LVPECL FIBR CLK RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| NB3N3002 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3.3V, Crystal-to-HCSL Clock Generator |
| NB3N3002DTG | 功能描述:鎖相環(huán) - PLL CLK GEN LVPECL DIFF OUT RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| NB3N3002DTR2G | 功能描述:鎖相環(huán) - PLL CLK GEN LVPECL DIFF OUT RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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