參數資料
型號: NAND128W3A0CZB1
廠商: 意法半導體
英文描述: 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
中文描述: 128兆,256兆,512兆位,1千兆位(x8/x16)528 Byte/264字的頁面,1.8V/3V,NAND閃存芯片
文件頁數: 19/57頁
文件大小: 410K
代理商: NAND128W3A0CZB1
19/57
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
COMMAND SET
All bus write operations to the device are interpret-
ed by the Command Interface. The Commands
are input on I/O0-I/O7 and are latched on the rising
edge of Write Enable when the Command Latch
Enable signal is high. Device operations are se-
lected by writing specific commands to the Com-
mand
sequences for program and erase operations are
imposed to maximize data security.
The Commands are summarized in
Table
9., Commands
.
Register.
The
two-step
command
Table 9. Commands
Note: 1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or input/output data are not shown.
2. Any undefined command sequence will be ignored by the device.
Command
Bus Write Operations
(1)
Command accepted
during busy
1
st
CYCLE
2
nd
CYCLE
3
rd
CYCLE
Read A
00h
-
-
Read B
01h
(2)
-
-
Read C
50h
-
-
Read Electronic Signature
90h
-
-
Read Status Register
70h
-
-
Yes
Page Program
80h
10h
-
Copy Back Program
00h
8Ah
10h
Block Erase
60h
D0h
-
Reset
FFh
-
-
Yes
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