參數(shù)資料
型號： MX29GL320ETTI-70G
廠商： MACRONIX INTERNATIONAL CO LTD
元件分類： PROM
英文描述： 2M X 16 FLASH 3V PROM, 70 ns, PDSO48
封裝： 14 X 20 MM, ROHS COMPLIANT, MO-142, TSOP1-48
文件頁數(shù)： 67/73頁
文件大?。?/td> 2630K
代理商： MX29GL320ETTI-70G
7
P/N:PM1509
REV. 1.1, DEC. 03, 2010
MX29GL320E T/B
MX29GL320E H/L
BLOCK DIAGRAM DESCRIPTION
TheblockdiagramonPage6illustratesasimplifiedarchitectureofthisdevice.Eachblockintheblockdiagram
representsoneormorecircuitmodulesintherealchipusedtoaccess,erase,program,andreadthememory
array.
The"CONTROLINPUTLOGIC"blockreceivesinputpinsCE#,OE#,WE#,RESET#,BYTE#,andWP#/ACC.
Itcreatesinternaltimingcontrolsignalsaccordingtotheinputpinsandoutputstothe"ADDRESSLATCHAND
BUFFER" to latch the external address pinsA0-AM.The internal addresses are output from this block to the
mainarrayanddecoderscomposedof"X-DECODER","Y-DECODER","Y-PASSGATE",AND"FLASHARRAY".
TheX-DECODERdecodestheword-linesoftheflasharray,whiletheY-DECODERdecodesthebit-linesofthe
flasharray.Thebitlinesareelectricallyconnectedtothe"SENSEAMPLIFIER"and"PGMDATAHV"selectively
throughtheY-PASSGATES.SENSEAMPLIFIERSareusedtoreadoutthecontentsoftheflashmemory,while
the"PGMDATAHV"blockisusedtoselectivelydeliverhighpowertobit-linesduringprogramming.The"I/O
BUFFER"controlstheinputandoutputontheQ0-Q15/A-1pads.Duringreadoperation,theI/OBUFFERre-
ceivesdatafromSENSEAMPLIFIERSanddrivestheoutputpadsaccordingly.Inthelastcycleofprogramcom-
mand,theI/OBUFFERtransmitsthedataonQ0-Q15/A-1to"PROGRAMDATALATCH",whichcontrolsthehigh
powerdriversin"PGMDATAHV"toselectivelyprogramthebitsinawordorbyteaccordingtotheuserinput
pattern.
The"PROGRAM/ERASEHIGHVOLTAGE"blockcomprisesthecircuitstogenerateanddeliverthenecessary
highvoltagetotheX-DECODER,FLASHARRAY,and"PGMDATAHV"blocks.Thelogiccontrolmodulecom-
prises of the "WRITE STATE MACHINE, WSM", "STATE REGISTER", "COMMAND DATA DECODER", and
"COMMANDDATALATCH".WhentheuserissuesacommandbytogglingWE#,thecommandonQ0-Q15/A-1
islatchedintheCOMMANDDATALATCHandisdecodedbytheCOMMANDDATADECODER.TheSTATE
REGISTERreceivesthecommandandrecordsthecurrentstateofthedevice.TheWSMimplementsthein-
ternalalgorithmsforprogramoreraseaccordingtothecurrentcommandstatebycontrollingeachblockinthe
blockdiagram.
ARRAY ARCHITECTURE
ThemainflashmemoryarraycanbeorganizedasBytemode(x8)orWordmode(x16).Thedetailsofthead-
dressrangesandthecorrespondingsectoraddressesareshowninTable1.
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