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參數(shù)資料
| 型號(hào)： | MVTX2602AG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | Managed 24 Port 10/100 Mbps Ethernet Switch |
| 中文描述： | DATACOM, LAN SWITCHING CIRCUIT, PBGA553 |
| 封裝： | 37.50 X 37.50 MM, 2.33 MM HEIGHT, MS-034, HSBGA-553 |
| 文件頁(yè)數(shù)： | 13/147頁(yè) |
| 文件大?。?/td> | 924K |
| 代理商： | MVTX2602AG |
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MVTX2602
Data Sheet
13
Zarlink Semiconductor Inc.
1.0 Block Functionality
1.1 Frame Data Buffer (FDB) Interfaces
The FDB interface supports pipelined synchronous burst SRAM (SBRAM) memory at 100 MHz. To ensure a non-
blocking switch, one memory domain with a 64 bit wide memory bus is required. At 100 MHz the aggregate
memory bandwidth is 6.4 Gbps which is enough to support 24 10/100 Mbps.
The Switching Database is also located in the external SRAM; it is used for storing MAC addresses and their
physical port number.
1.2 10/100 MAC Module (RMAC)
The 10/100 Media Access Control module provides the necessary buffers and control interface between the
Frame Engine (FE) and the external physical device (PHY). The MVTX2602 has two interfaces, RMII or Serial
(only for 10 M). The 10/100 MAC of the MVTX2602 device meets the IEEE 802.3 specification. It is able to operate
in either Half or Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically
retransmit upon collision for up to 16 total transmissions. The PHY addresses for the 24 10/100 MACs are from
08h to 1Fh.
1.3 CPU Interface Module
One extra port is dedicated to the CPU via the CPU interface module. The CPU interface utilizes a 16/8-bit bus in
managed mode (Bootstrap pin TSTOUT6 makes the selection). It also supports a serial and an I2C interface which
provides an easy way to configure the system if unmanaged.
1.4 Management Module
The CPU can send a control frame to access or configure the internal network management database. The
Management Module decodes the control frame and executes the functions requested by the CPU.
1.5 Frame Engine
The main function of the frame engine is to forward a frame to its proper destination port or ports. When a frame
arrives the frame engine parses the frame header (64 bytes) and formulates a switching request which is sent to
the search engine to resolve the destination port. The arriving frame is moved to the FDB. After receiving a switch
response from the search engine the frame engine performs transmission scheduling based on the frame’s
priority. The frame engine forwards the frame to the MAC module when the frame is ready to be sent.
1.6 Search Engine
The Search Engine resolves the frame’s destination port or ports according to the destination MAC address (L2) or
IP multicast address (IP multicast packet) by searching the database. It also performs MAC learning, priority
assignment and trunking functions.
1.7 LED Interface
The LED interface provides a serial interface for carrying 24 port status signals.
1.8 Internal Memory
Several internal tables are required and are described as follows:
Frame Control Block (FCB) - Each FCB entry contains the control information of the associated frame
stored in the FDB, e.g., frame size, read/write pointer, transmission priority, etc.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MVTX2603 | Unmanaged 24-Port 10/100 Mb + 2-Port 1 Gb Ethernet Switch |
| MVTX2603AG | Unmanaged 24-Port 10/100 Mb + 2-Port 1 Gb Ethernet Switch |
| MVTX2604 | Managed 24-Port 10/100 Mb + 2 Port 1 Gb Ethernet Switch |
| MVTX2604AG | Managed 24-Port 10/100 Mb + 2 Port 1 Gb Ethernet Switch |
| MVTX2801 | Unmanaged 4-Port 1000 Mbps Ethernet Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MVTX2602AG2 | 制造商:Microsemi Corporation 功能描述: |
| MVTX2603 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Unmanaged 24-Port 10/100 Mb + 2-Port 1 Gb Ethernet Switch |
| MVTX2603A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Unmanaged 24 port 10/100Mb + 2 port 1Gb Ethernet switch |
| MVTX2603AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Unmanaged 24-Port 10/100 Mb + 2-Port 1 Gb Ethernet Switch |
| MVTX2603AG2 | 制造商:Microsemi Corporation 功能描述: |
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