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參數資料
| 型號： | MT93L04AG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數字傳輸電路 |
| 英文描述： | 128-Channel Voice Echo Canceller |
| 中文描述： | DATACOM, ISDN ECHO CANCELLER, PBGA365 |
| 封裝： | 27 X 27 MM, 2.33 MM HEIGHT, MS-034, BGA-365 |
| 文件頁數： | 45/56頁 |
| 文件大?。?/td> | 903K |
| 代理商： | MT93L04AG |
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MT93L04
Data Sheet
45
Zarlink Semiconductor Inc.
6
ODE
Output Data Enable: This control bit is logically AND’d with the ODE input pin. When
both ODE bit and ODE input pin are high, the Rout and Sout outputs are enabled.
When the ODE bit is low or the ODE input pin is low, the Rout and Sout outputs are
high impedance
.
Note:
Only the
Main Control Register 0
has the ODE bit.
5
MIRQ
Mask Interrupt: When high, all the interrupts from the Tone Detectors output are
masked. The Tone Detectors operate as specified in their Echo Canceller B, Control
Register 2.
When low, the Tone Detectors Interrupts are active.
Note:
Only the
Main Control Register 0
has the MIRQ bit.
4
MTDBI
Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from
Echo Canceller B is masked. The Tone Detector operates as specified in Echo
Canceller B, Control Register 2.
When low, the Tone Detector B Interrupt is active.
3
MTDAI
Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from
Echo Canceller A is masked. The Tone Detector operates as specified in Echo
Canceller A, Control Register 2.
When low, the Tone Detector A Interrupt is active.
2
Format
ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, accept
ITU-T (G.711) PCM code.
When low, both Echo Cancellers A and B for a given group, accept sign-magnitude
PCM code
.
1
LAW
A/
μ
Law: When high, both Echo Cancellers A and B for a given group, accept A-Law
companded PCM code.
When low, both Echo Cancellers A and B for a given group, accept
μ
-Law companded
PCM code.
0
PWUP
Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given
group, are active.
When low, both Echo Cancellers A and B and Tone Detectors for a given group, are
placed in Power Down mode. In this mode, the corresponding PCM data are bypassed
from Rin to Rout and from Sin to Sout with two frames delay.
When the PWUP bit toggles from zero to one, the echo canceller A and B execute their
initialization routine which presets their registers, Base Address+00H to Base
Address+3FH, to default Reset Value and clears the Adaptive Filter coefficients.
Two frames are necessary for the initialization routine to execute properly. Once the
initialization routine is executed, the user can set the per channel Control Registers for
their specific application.
Bit
Name
Description
Main Control Register 0
(EC group 0)
Read/Write Address: 400
H
PWUP
LAW
Format
MTDAI
MTDBI
MIRQ
ODE
WR_all
7
6
5
4
3
2
1
0
Reset Value:
00
H
.
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