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參數(shù)資料
| 型號(hào)： | MT93L04 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 128-Channel Voice Echo Canceller |
| 中文描述： | 128頻道語音回聲消除器 |
| 文件頁數(shù)： | 44/56頁 |
| 文件大小： | 903K |
| 代理商： | MT93L04 |
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MT93L04
Data Sheet
44
Zarlink Semiconductor Inc.
Bit
Name
Description
7
WR_all
Write all control bit: When high, Group 0-15 Echo Cancellers Registers are mapped
into 0000h to 0003Fh which is Group 0 address mapping. Useful to initialize the 16
Groups of Echo Cancellers as per Group 0.
When low, address mapping is per Figure 8.
Note:
Only the
Main Control Register 0
has the WR_all bit.
Power Reset Value
0Bh
7
6
5
4
3
2
1
0
NLP15
NLP14
NLP13
NLP12
NLP10
NLP9
NLP8
NLP11
Echo Canceller A, Non-Linear Processor Threshold Register 2
Read/Write Address:
19h
+ Base Address
Echo Canceller B, Non-Linear Processor Threshold Register 2
Read/Write Address:
39h
+ Base Address
Power Reset Value
60h
7
6
5
4
3
2
1
0
NLP7
NLP6
NLP5
NLP4
NLP2
NLP1
NLP0
NLP3
Echo Canceller A, Non-Linear Processor Threshold Register 1
Read/Write Address:
18h
+ Base Address
Echo Canceller B, Non-Linear Processor Threshold Register 1
Read/Write Address:
38h
+ Base Address
This register allows the user to program the level of the Non-Linear Processor Threshold (NLPTHR). The
16 bit 2’s complement linear value defaults to 0B60h = 0.0889 or -21.0 dB. The maximum value is 7FFFh =
0.9999 or 0 dB. The high byte is in Register 2 and the low byte is in Register 1.
(NLPTHR)
(NLPTHR)
Power Reset Value
40h
7
6
5
4
3
2
1
0
MU15
MU14
MU13
MU12
MU10
MU9
MU8
MU11
Echo Canceller A, Adaptation Step Size (MU) Register 2
Echo Canceller B, Adaptation Step Size (MU) Register 2
Read/Write Address:
1Bh
+ Base Address
Read/Write Address:
3Bh
+ Base Address
Power Reset Value
00h
7
6
5
4
3
2
1
0
MU7
MU6
MU5
MU4
MU2
MU1
MU0
MU3
Echo Canceller A, Adaptation Step Size (MU) Register 1
Echo Canceller B, Adaptation Step Size (MU) Register 1
Read/Write Address:
1Ah
+ Base Address
Read/Write Address:
3Ah
+ Base Address
This register allows the user to program the level of MU. MU is a 16 bit 2’s complement value which defaults
to 4000h = 1.0
The maximum value is 7FFFh or 1.9999 decimal. The high byte is in Register 2 and the low byte is in
Register 1.
(MU)
(MU)
Main Control Register 0
(EC group 0)
Read/Write Address: 400
H
PWUP
LAW
Format
MTDAI
MTDBI
MIRQ
ODE
WR_all
7
6
5
4
3
2
1
0
Reset Value:
00
H
.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT93L04A | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:128-Channel Voice Echo Canceller |
| MT93L04AG | 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 128CH G.164/G.165/G.168/G.711 W/ TONE DE - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC VOICE ECHO CANCEL 365MCMBGA |
| MT93L04AG2 | 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 128CH G.164/G.165/G.168/G.711 W/ TONE DE - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC VOICE ECHO CANCEL 365MCMBGA 制造商:Microsemi Corporation 功能描述:IC VOICE ECHO CANCEL 365MCMBGA |
| MT93L16 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:AEC with Noise Reduction & Codecs for Digital Hands-Free Communication |
| MT93L16AF | 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 2CH G.711 W/OUT TONE DETECTION 48TQFP - Rail/Tube |
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