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MT93L00A
Data Sheet
11
Zarlink Semiconductor Inc.
Offset Null Filter
Adaptive filters in general do not operate properly when a DC offset is present at any inputs. To remove the DC
component, the MT93L00 incorporates Offset Null filters in both Rin and Sin inputs.
The offset null filters can be disabled by setting the HPFDis bit to “1” in Control Register 2.
ITU-T G.168 Compliance
The MT93L00 has been certified G.168 compliant in all 64 ms cancellation modes (i.e. Normal and Back-to-Back
configurations) by in-house testing with the DSPG ECT-1 echo canceller tester.
It should be noted that G.168 compliance is not claimed for the 128 ms Extended Delay mode, although
subjectively no difference can be noticed.
Device Configuration
The MT93L00 architecture contains 32 echo cancellers divided into 16 groups. Each group has two echo cancellers
which can be individually controlled (Echo Canceller A and B). They can be set in three distinct configurations:
Normal, Back-to-Back,
and
Extended Delay
. See Figure 6.
Normal Configuration
In Normal configuration, the two echo cancellers (Echo Canceller A and B) are positioned in parallel, as shown in
Figure 6a, providing 64 milliseconds of echo cancellation in two channels simultaneously.
Back-to-Back Configuration
In Back-to-Back configuration, the two echo cancellers from the same group are positioned to cancel echo coming
from both directions in a single channel providing full-duplex 64 ms echo cancellation. See Figure 6c. This
configuration uses only one timeslot on PORT1 and PORT2 and the second timeslot normally associated with ECB
contains undefined data. Back-to-Back configuration allows a no-glue interface for applications where bidirectional
echo cancellation is required.
Back-to-Back configuration is selected by writing “1” into the BBM bit of
both
Control Register A1 and Control
Register B1 of a given group of echo cancellers. Table 2 shows the 16 groups of 2 cancellers that can be configured
into Back-to-Back.
Examples of Back-to-Back configuration include positioning one group of echo cancellers between a CODEC and a
transmission device or between two codecs for echo control on analog trunks.
Extended Delay configuration
In this configuration, the two echo cancellers from the same group are internally cascaded into one 128
milliseconds echo canceller. See Figure 6b. This configuration uses only one timeslot on PORT1 and PORT2 and
the second timeslot normally associated with ECB contains undefined data.
Extended Delay configuration is selected by writing “1” into the ExtDl bit in Echo Canceller A, Control Register A1.
For a given group, only Echo Canceller A, Control Register A1, has the ExtDl bit. Control Register B1, bit-0 must
always be set to zero.
Table 2 shows the 16 groups of 2 cancellers that can each be configured into 64 ms or 128 ms echo tail capacity.