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參數(shù)資料
| 型號： | MT91L62 |
| 廠商： | Mitel Networks Corporation |
| 元件分類： | Codec |
| 英文描述： | 3 Volt Single Rail Codec(3V 單軌編解碼器) |
| 中文描述： | 3伏單鐵編解碼器（3V的單軌編解碼器） |
| 文件頁數(shù)： | 4/17頁 |
| 文件大小： | 79K |
| 代理商： | MT91L62 |
MT91L62
Advance Information
7-176
Table 2: Bit Clock Rate Selection
TxMute pin is high. When either of these pins are low
their respective paths function normally. The -Zero
entry of Table 1 is used for the quiet code definition.
SSI Mode
The SSI BUS consists of input and output serial data
streams named Din and Dout respectively, a Clock
input signal (CLOCKin), and a framing strobe input
(STB). A 4.096 MHz master clock is also required for
SSI operation if the bit clock is less than 512 kHz.
The timing requirements for SSI are shown in
Figures 5 & 6.
In SSI mode the MT91L62 supports only B-Channel
operation. Hence, in SSI mode transmit and receive
B-Channel data are always in the channel defined by
the STB input.
The data strobe input STB determines the 8-bit
timeslot used by the device for both transmit and
receive data. This is an active high signal with an 8
kHz repetition rate.
SSI operation is separated into two categories based
upon the data rate of the available bit clock. If the bit
clock is 512 kHz or greater then it is used directly by
the
internal
MT91L62
synchronous operation. If the available bit clock is
128 kHz or 256 kHz, then a 4096 kHz master clock is
required to derive clocks for the internal MT91L62
functions.
functions
allowing
Applications where Bit Clock (BCL) is below 512 kHz
are designated as asynchronous. The MT91L62 will
re-align its internal clocks to allow operation when
the external master and bit clocks are asynchronous.
Control pins CSL2, CSL1 and CSL0 are used to
program the bit rates.
For synchronous operation, data is sampled from
Din, on the falling edge of BCL during the time slot
defined by the STB input. Data is made available, on
CSL
2
CSL
1
CSL
0
External
Clock Bit
Rate
(kHz)
CLOCKin
(kHz)
1
0
0
128
4096
1
0
1
256
4096
0
0
0
512
512
0
0
1
1536
1536
0
1
0
2048
2048
0
1
1
4096
4096
Figure 3 - Audio Gain Partitioning
Serial
Port
Filter/Codec and Analog Interface
PCM
D
in
Receive
Filter Gain
0 dB
Receiver
Driver
0 dB
Aout +
Aout-
20k
Internal To Device
External To Device
Default Bypass
AIN+
AIN-
Transmit Gain
6 dB
PCM
Analog
Input
D
out
Decoder
Encoder
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MT91L62AE | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO2-CMOS 3 Volt Single Rail Codec |
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| MT91L62AS | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO2-CMOS 3 Volt Single Rail Codec |
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