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參數(shù)資料
| 型號： | MT9196ASR1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Integrated Digital Phone Circuit (IDPC) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO28 |
| 封裝： | 0.300 INCH, LEAD FREE, MS-013AE, SOIC-28 |
| 文件頁數(shù)： | 23/46頁 |
| 文件大?。?/td> | 631K |
| 代理商： | MT9196ASR1 |
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MT9196
Data Sheet
23
Zarlink Semiconductor Inc.
Note: Bits marked "-" are reserved bits and should be written with logic "0".
ST-BUS/SSI
CEN
When high, the FDI port operates in ST-BUS mode. When low, the FDI operates in SSI mode.
When high, data written into the C-Channel register (address 14h) are transmitted during channel 1 on DSTo.
When low, the channel 1 timeslot is tri-stated on DSTo. Channel 1 data received on DSTi is read via the C-
Channel register (address 14h) regardless of the state of CEN. This control bit has significance only for ST-BUS
operation and is ignored for SSI operation.
When high, data written into the D-Channel Register (address 15h) are transmitted during channel 0 on DSTo.
When low, the channel 0 timeslot is tri-stated on DSTo. Channel 0 data received on DSTi is read via the D-
Channel register regardless of the state of DEN. This control bit has significance only for ST-BUS mode and is
ignored for SSI operation.
When high, the D-Channel operates at 8 kb/s.
When low, the D-Channel operates at 16 kb/s default.
Control bits Asynch/Synch, CSL
1
and CSL
0
are used to program the data clock (BCL) bit rates as shown in the
following table (CSL
1
and CSL
0
are ignored in ST-BUS mode):
DEN
D8
Asynch/Synch,
CSL
1
,CSL
0
Asynch/Synch
CSL
1
CSL
0
Bit Clock Rate (kHz)
CLOCKin (kHz)
1
0
0
128
4096 mandatory
1
0
1
256
4096 mandatory
0
0
0
512
512
0
0
1
1536
1536
0
1
0
2048
2048
0
1
1
4096
4096
FDI Control Register
ADDRESS = 10h WRITE/READ VERIFY
Power Reset Value
X000 0000
7
6
5
4
3
2
1
0
-
ST-BUS/
CEN
SSI
DEN
Asynch/
Synch
CSL
1
CSL
0
D8
Note: Asynch/Synch must be set low for ST-BUS operation
Watchdog Register
ADDRESS = 11h WRITE
Power Reset Value
XXXX XXXX
7
6
5
4
3
2
1
0
-
-
-
0
0
1
0
1
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