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參數資料
| 型號： | MT9173AN1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數字傳輸電路 |
| 英文描述： | Digital Subscriber Interface Circuit with RxSB Digital Network Interface Circuit with RxSB |
| 中文描述： | DATACOM, DIGITAL SLIC, PDSO24 |
| 封裝： | 5.30 MM, LEAD FREE, MO-150AG, SSOP-24 |
| 文件頁數： | 20/28頁 |
| 文件大?。?/td> | 613K |
| 代理商： | MT9173AN1 |
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MT9173/74
Data Sheet
20
Zarlink Semiconductor Inc.
Figure 16 - C4 Clock & Frame Pulse Alignment for ST-BUS Streams in DN Mode
Figure 17 - Frequency Locking for the C4 and OSC1 Clocks in MAS/DN Mode
Timing is over recommended temperature & power supply voltage ranges.
* Typical figures are at 25
°
C, for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics
- Clock Timing - MOD Mode (Figure 18)
Characteristics
Sym
80 kbit/s
160 kbit/s
Units
Test
Conditions
Min.
Typ.*
Max. Min.
Typ.*
Max.
1 TCK/RCK Clock Period
2 TCK/RCK Clock Width
3 TCK/RCK Clock Transition Time
t
CP
t
CW
t
CT
t
CLDS
t
CLDH
t
CLDW
t
CLDP
12.5
6.25
6.25
3.125
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
20
20
C
L
=40 pF
4 CLD to TCK Setup Time
3.125
1.56
5 CLD to TCK Hold Time
3.125
1.56
6 CLD Width Low
6.05
2.925
7 CLD Period
8
x
t
CP
8
x
t
CP
C4
F0
2.0 V
0.8 V
2.0 V
0.8 V
t
C4P
t
C4W
t
F0S
t
F0H
t
F0W
t
C4W
C4
OSC1
2.0 V
0.8 V
3.0 V
2.0 V
J
C
F
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