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參數(shù)資料
| 型號(hào)： | MT9171APR |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Digital Subscriber Interface Circuit Digital Network Interface Circuit |
| 中文描述： | DATACOM, DIGITAL SLIC, PQCC28 |
| 封裝： | PLASTIC, MS-018AB, LCC-28 |
| 文件頁數(shù)： | 21/28頁 |
| 文件大小： | 552K |
| 代理商： | MT9171APR |
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MT9171/72
Data Sheet
21
Zarlink Semiconductor Inc.
Timing is over recommended temperature & power supply voltage ranges.
* Typical figures are at 25
°
C, for design aid only: not guaranteed and not subject to production testing.
Figure 18 - RCK, TCK & CLD Timing For MOD Mode
AC Electrical Characteristics
- Clock Timing - MOD Mode (Figure 18)
Characteristics
Sym.
80 kbit/s
160 kbit/s
Units
Test
Conditions
Min.
Typ.*
Max.
Min.
Typ.*
Max.
1
TCK/RCK Clock Period
t
CP
12.5
6.25
ms
2
TCK/RCK Clock Width
t
CW
6.25
3.125
ms
3
TCK/RCK Clock Transition
Time
t
CT
20
20
ns
C
L
=40pF
4
CLD to TCK Setup Time
t
CLDS
3.125
1.56
ms
5
CLD to TCK Hold Time
t
CLDH
3.125
1.56
ms
6
CLD Width Low
t
CLDW
6.05
2.925
ms
7
CLD Period
t
CLDP
8
x
t
CP
8
x
t
CP
ms
RCK
TCK
CLD
t
CT
t
CP
t
CLDS
t
CLDH
t
CW
t
CT
t
CLDW
t
CW
2.4V
0.4V
2.4V
0.4V
2.4V
0.4V
t
CP
Note 1:
TCK and CLD are generated on chip and provide the data clocks for the CD port and the transmit section of the
DV port. RCK, also generated on chip, is extracted from the receive data and only clocks out the data at the D
o
output
and may be skewed with respect to TCK due to end-to-end delay.
At the slave end TCK is phase locked to RCK.
The rising edge of TCK will lead the rising edge of RCK by approximately 90
o
.
Note 2:
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT9171APR1 | 制造商:Microsemi Corporation 功能描述:PB FREE 1.5UM DNIC - Tape and Reel 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE 1.5UM DNIC - Tape and Reel |
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| MT9172AE | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:ISO2-CMOS ST-BUS FAMILY |
| MT9172AE1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Subscriber Interface Circuit Digital Network Interface Circuit |
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