參數(shù)資料
型號(hào): MT9172
廠商: Zarlink Semiconductor Inc.
英文描述: Digital Subscriber Interface Circuit Digital Network Interface Circuit
中文描述: 數(shù)字用戶接口電路數(shù)字網(wǎng)絡(luò)接口電路
文件頁(yè)數(shù): 1/28頁(yè)
文件大?。?/td> 552K
代理商: MT9172
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1999-2006, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Full duplex transmission over a single twisted pair
Selectable 80 or 160 kbit/s line rate
Adaptive echo cancellation
Up to 3 km (9171) and 4 km (9172)
ISDN compatible (2B+D) data format
Transparent modem capability
Frame synchronization and clock extraction
Zarlink ST-BUS compatible
Low power (typically 50 mW), single 5 V supply
Applications
Digital subscriber lines
High speed data transmission over twisted wires
Digital PABX line cards and telephone sets
80 or 160 kbit/s single chip modem
Description
The
MT9171 (DSIC) and MT9172 (DNIC) are pin for
pin compatible replacements for the MT8971 and
MT8972, respectively. They are multi-function devices
capable of providing high speed,
full duplex digital
transmission up to 160 kbit/s over a twisted wire pair.
They use adaptive echo-cancelling techniques and
transfer data in (2B+D) format compatible to the ISDN
basic rate. Several modes of operation allow an easy
interface to digital telecommunication networks
including use as a high speed limited distance modem
March 2006
Ordering Information
22 Pin PDIP
24 Pin SSOP
28 Pin PLCC
28 Pin PLCC
24 Pin SSOP
22 Pin PDIP*
28 Pin PLCC*
24 Pin SSOP*
28 Pin PLCC*
24 Pin SSOP*
*Pb Free Matte Tin
-40
°
C to +85
°
C
MT9171/72AE
MT9171/72AN
MT9171/72AP
MT9171/72APR
MT9171/72ANR
MT9171/72AE1
MT9171/72AP1
MT9171/72AN1
MT9171/72APR1
MT9171/72ANR1
Tubes
Tubes
Tubes
Tape & Reel
Tape & Reel
Tubes
Tubes
Tubes
Tape & Reel
Tape & Reel
ISO
2
-CMOS ST-BUS
FAMILY MT9171/72
Digital Subscriber Interface Circuit
Digital Network Interface Circuit
Data Sheet
Figure 1 - Functional Block Diagram
DSTi/Di
CDSTi/
CDi
F0/CLD
C4/TCK
F0o/RCK
MS0
MS1
MS2
RegC
DSTo/Do
CDSTo/
CDo
Transmit
Interface
Prescrambler
Scrambler
Control
Register
Transmit/
Clock
Receive
Timing &
Control
Status
Transmit
Timing
Master Clock
Phase Locked
Sync Detect
Receive
DPLL
Receive
Interface
De
-
Prescrambler
Descrambler
Differentially
Encoded Biphase
Receiver
Differentially
Encoded
Biphase
Transmitter
Transmit
Filter &
Line Driver
Receive
Filter
-1
+2
MUX
Address
Echo Canceller
Error
Signal
Echo Estimate
V
Bias
V
DD
V
SS
V
Bias
V
Ref
L
OUT
L
OUT
DIS
Precan
L
IN
OSC2
OSC1
+
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