參數(shù)資料
型號(hào): MT9171AP1
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數(shù)字傳輸電路
英文描述: Digital Subscriber Interface Circuit Digital Network Interface Circuit
中文描述: DATACOM, DIGITAL SLIC, PQCC28
封裝: LEAD FREE, PLASTIC, MS-018AB, LCC-28
文件頁(yè)數(shù): 22/28頁(yè)
文件大?。?/td> 552K
代理商: MT9171AP1
MT9171/72
Data Sheet
22
Zarlink Semiconductor Inc.
Timing is over recommended temperature & power supply voltage ranges.
Figure 19 - Data Timing For DN Mode
Timing is over recommended temperature & power supply voltage ranges.
* Typical figures are at 25
°
C, for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics
- Data Timing - DN Mode (Figure 19)
Characteristics
Sym.
Min.
Typ.*
Max.
Units
Test Conditions
1
DSTi/CDSTi Data Setup Time
t
RS
t
RH
t
TD
t
ZTD
30
ns
2
DSTi/CDSTi Data Hold Time
50
ns
3a
DSTo/CDSTo Data Delay
120
ns
C
L
=40pF
C
L
=40pF
3b
DSTo/CDSTo High Z to Data Delay
140
ns
AC Electrical Characteristics
- Data Timing - MOD Mode (Figure 20)
Characteristics
Sym.
80 kbit/s
Min.
150
4.5
160 kbit/s
Units
Test
Conditions
Typ.*
Max. Min.
Typ.*
Max.
1
2
3
4
Di/CDi Data Setup Time
Di/CDi Data Hold Time
Do Data Delay Time
CDo Data Delay Time
t
DS
t
DH
t
RD
t
TD
150
2.5
ns
μ
s
ns
ns
70
70
70
70
C
L
=40pF
C
L
=40pF
Performance Characteristics of the MT9171 DSIC
Characteristics
1
Allowable Attenuation for Bit Error
Rate of 10
-6
(Note 1)
2
Line Length at 80 kbit/s
Sym.
A
fb
Min.
0
Typ.*
30
Max.
25
Units
dB
Test Conditions
SNR16.5dB (300kHz
bandlimited noise)
attenuation - 6.9 dB/km
attenuation - 10.0 dB/km
attenuation - 8.0 dB/km
attenuation - 11.5 dB/km
-24 AWG
-26 AWG
L
80
3.0
2.2
3.0
2.2
km
3
Line Length at 160 kbit/s -24 AWG
-26 AWG
L
160
km
2.0V
0.8V
2.4V
0.4V
2.0V
0.8V
Bit
Stream
C4
DSTi
CDSTi
DSTo
CDSTo
Bit Cell
t
TD
t
RS
t
RH
t
TD
t
ZTD
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