- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359677 > MT90882IG (Zarlink Semiconductor Inc.) TDM to Packet Processors PDF資料下載
參數(shù)資料
| 型號： | MT90882IG |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | TDM to Packet Processors |
| 中文描述： | TDM到分組處理器 |
| 文件頁數(shù)： | 76/97頁 |
| 文件大?。?/td> | 702K |
| 代理商： | MT90882IG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁當(dāng)前第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁
MT90880/1/2/3
Data Sheet
76
Zarlink Semiconductor Inc.
6.13 DPLL Specification
The MT9088x contains an internal Digital Phase Locked Loop (DPLL) which exceeds the requirements of
Stratum 4E. This is provided both to synchronise to external references and generate the internal clocks
required by the device when operating in synchronous mode.
The DPLL accepts two references, primary and secondary, selected from the incoming ports on the WAN
Access Interface. Failure of a reference is automatically detected, and the DPLL can switch between references
without introducing bit errors. Reference switching can be performed under automatic or manual control.
The DPLL operates in two main modes, "Master" and "Slave". In Master mode, the DPLL accepts an incoming
8KHz frame reference, and generates a stable, low jitter clock and frame pulse for the selected data format.
Master mode is generally used where the MT9088x is supplying the clocks to the TDM infrastructure, for
example, T1/E1 framers, or a TDM backplane such as H.110 or H-MVIP.
In
Slave
mode, both the incoming and outgoing streams are timed using the external reference, bypassing the
DPLL. The DPLL locks to both the clock and the frame pulse, and generates the internal clocking for the device.
This mode is used where the master clock and frame references are provided externally.
Features include:
Exceeds Stratum 4E standard
Three fundamental modes of operation:
"Master" clock-generator mode - locks to incoming 8KHz frame reference
"Slave" clock-follower mode - locks to incoming clock and frame reference
"Free-run" mode allows clock generation without an external reference
Primary and secondary references
Automatic detection of reference failure
Holdover operation, maintaining last locked reference frequency
Error-free reference switching, meeting
Telcordia GR-1244-CORE (reference 10, Table 3)
6.13.1 Master Mode
In master mode, the DPLL locks to an incoming 8KHz frame reference. It generates the clock and frame pulses
required by the selected data format on the WAN Access Interface (see Table 7 on page 16). From a device
reset condition or after a reference switch, the DPLL will take up to 50 seconds to phase lock the output signals
to the selected input reference signal.
Primary and Secondary References
The DPLL can operate with two references, a primary and a secondary, selected from any of input frame
references. The health of both selected references is continuously monitored. When an incoming reference
fails, the DPLL can either automatically switch to the alternate reference, or enter holdover operation. The
reference switch can then be manually controlled. Should the failed reference return, the device will re-lock to
the reference. The DPLL provides bit error free reference switching, meeting the phase slope and MTIE
requirements defined by the Telcordia GR-1244-CORE standard (reference 10, Table 3).
Holdover Operation
In Holdover, the DPLL maintains the clock frequency at the value recorded before the reference was judged to
have failed. Holdover is typically used for short durations while network synchronization is temporarily
disrupted. The initial accuracy of the held frequency is
±
0.06 ppm, which translates in the worst case to 42
frame (125
μ
s) slips in 24 hours.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90883A | TDM to Packet Processors |
| MT90883IG | TDM to Packet Processors |
| MT9088IG | TDM to Packet Processors |
| MT8960 | Integrated PCM Filter Codec |
| MT8963AE1 | Integrated PCM Filter Codec |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90883 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90883A | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90883A/IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90883BP1N | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90883IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。