參數(shù)資料
型號(hào)： MT90840AL
廠(chǎng)商： ZARLINK SEMICONDUCTOR INC
元件分類(lèi)： 路由/交換
英文描述： Distributed Hyperchannel Switch
中文描述： TELECOM, DIGITAL TIME SWITCH, PQFP100
封裝： 14 X 20 MM, 2.80 MM HEIGHT, MO-112CC-1, MQFP-100
文件頁(yè)數(shù)： 16/51頁(yè)
文件大?。?/td> 512K
代理商： MT90840AL
MT90840
Data Sheet
2-246
Table 1 - MT90840 Throughput Delay Summary
Naming rules:
ELD: ELastic Delay, measured from PPFRi to F0i (4.4 to 129.4
μ
sec).
P/S:Parallel-to-Serial data path.
Pi:Parallel Input channel time, expressed in delay after PPFRi (0 to 125
μ
sec).
Po:Parallel Output channel time, expressed in delay after PPFTi/o (0 to 125
μ
sec).
S/P:Serial-to-Parallel data path.
Si:Serial Input channel time, expressed in delay after F0i/o (0 to 125
μ
sec).
So: Serial Output channel time, expressed in delay after F0i/o (0 to 125
μ
sec).
Transmission:The delay due to electronic circuits and physical media connecting the parallel ports of two MT90840s. (Assumed to be
negligible in TM3.)
Note 1: Exact P/S or S/P delay depends on relative positions of PPFRi and F0 +/- 120 nsec tolerance).
Note 2: Actual TM1 P/S and P/P delay depends on elastic position of PPFRi with respect to F0i (see ELD definition).
Note 3: Bypass delay in TM2: PPFT and PDo ch.0 are co-incident with PDi ch.235 at 19.44 MHz, ch.199 at 16 MHz, and ch.80 at 6.48
MHz. (TCP = 1 delays PDo ch.0 an extra half clock-cycle in TM2).
Note 4: “Round-trip” delay from/to serial ports with the same F0 is always an integral number of frames (plus switching: So - Si).
Mode
Data Rates
Minimum Delay
Total Throughput Delay
TM1, TM2,
or TM3 S/P
All
Dmin = 7.7
μ
sec
Note 1
D = Dmin + 1 frame + Po - Si = 132.7
μ
sec + Po - Si
Min. 7.7
μ
sec, Avg. 133
μ
sec, Max. 258
μ
sec
TM1P/S
All
Dmin = ELDmin
= 4.4
μ
sec
Note 2
D = 1 frame + ELD + So - Pi = 125
μ
sec + ELD + So - Pi
Min. 4.4
μ
sec, Max. 379
μ
sec
TM2 P/S
All
Dmin = 4.3
μ
sec
Note 1
D = Dmin + 1 frame + So - Pi = 129.3
μ
sec + So - Pi
Min. 4.3
μ
sec, Avg. 129
μ
sec, Max. 254
μ
sec
TM3 P/S
All
Dmin = 1 frame -
7.7
μ
sec
= 117.3
μ
sec
T = Dmin + 1 frame + So - Pi = 242.3
μ
sec + So - Pi
Min. 117
μ
sec, Avg. 242
μ
sec, Max. 367
μ
sec
TM1 P/P
(Bypass)
All
Dmin = 12
μ
sec +
1 frame
= 137
μ
sec
Note 2
D = 7.7
μ
sec + 1 frame + ELD
Min.137
μ
sec, Max. 262
μ
sec
TM2 P/P
(Bypass)
19.44 Mbyte/s
16.384 Mbyte/s
6.480 Mbyte/s
Note 3
D = {235 or 235.5} PCKR cycles = 12
μ
sec
D = {199 or 199.5} PCKR cycles = 12
μ
sec
D = {80 or 80.5} PCKR cycles = 12
μ
sec
TM4 P/P
(Switching)
19.44 & 16.384
Mbyte/s
Dmin = {3.5 or 4}
PCKR cycles
(TCP bit = 1 or 0)
D = Dmin + 1 frame + Po - Pi
Min. < 0.3
μ
sec, Avg. 125
μ
sec, Max. 250
μ
sec
TM1 S/P +
TM2 P/S
All
Dmin = 12
μ
sec +
1 frame
= 137
μ
sec
D = 12
μ
s + 2 frames + Transmission + So - Si
= 262
μ
sec + Transmission + So - Si
TM2 S/P +
TM1 P/S
All
Dmin = 12
μ
sec +
1 frame
= 137.4
μ
sec
D = 12
μ
sec + 2 frames + Transmission + ELD + So - Si
= 262
μ
sec + Transmission + ELD + So - Si
TM1 S/P +
TM2 P/S +
TM2 S/P +
TM1 P/S
All
Dmin = 4 frames
= 500
μ
sec
D = (2 X 12)
μ
sec + 4 frames + 2 X Transmission + ELD
+ So - Si = {5 or more integral frames} + So - Si
(Note 4)
TM1 S/P +
TM2
Bypass +
TM1 P/S
All
Dmin = 2 frames
= 250
μ
sec
D = (3 X 12)
μ
sec + 2 frames + 2 X Transmission + ELD
+ So - Si
= {3 or more integral frames} + So - Si
(Note 4)
TM3 S/P +
TM3 P/S
All
Dmin = 250
μ
sec
D = (7.7 + 117.3)
μ
sec + 2 frames + So - Si
= 375
μ
sec + So - Si
Min. 250
μ
sec, Avg. 375
μ
sec, Max. 500
μ
sec (Note 4)
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