參數(shù)資料
型號(hào): MT90840AL
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Distributed Hyperchannel Switch
中文描述: TELECOM, DIGITAL TIME SWITCH, PQFP100
封裝: 14 X 20 MM, 2.80 MM HEIGHT, MO-112CC-1, MQFP-100
文件頁(yè)數(shù): 1/51頁(yè)
文件大小: 512K
代理商: MT90840AL
2-231
Features
Time slot interchange function between eight
pairs of ST-BUS/GCI/MVIP
streams (512
channels) and parallel data port
Programmable data rates on the parallel port
(19.44, 16.384, or 6.480 Mbyte/s)
Programmable data rates on the serial port (2.048
Mbps, 4.096 Mbps or 8.192 Mbps)
Supports star and point-to-point connections, and
unidirectional or bidirectional ring topologies for
distributed systems
Input-to-output bypass function on the parallel
data port for use in add/drop applications
Provides elastic buffer at parallel input port in the
receive direction
Provides byte switching for up to 2430 channels
Per-channel direction control on the serial port
side
Per-channel message mode and high-impedance
control on both parallel and serial port sides
8-bit multiplexed microprocessor port compatible
with Intel and Motorola microcontrollers
Guarantees frame integrity when switching nX64
wideband channels such as ISDN H0 channel
Provides external control lines allowing fast
parallel interface to be shared with other devices
Diagnostic alarm functions and clock
phase-status word for clock monitoring
IEEE 1149 (JTAG) boundary scan port
Applications
Bridging ST-BUS/MVIP buses to high speed
Time Division Multiplexed backplanes at
SONET rates (STS-1, STS-3)
High speed isochronous backbones for
distributed PBX and LAN systems
Switch platforms of up to 2430 channels with
guaranteed frame integrity for wideband
channels
Serial bus control and monitoring
Data multiplexing
High speed communications interface
ISSUE 3
July 2002
Ordering Information
MT90840AL
100 Pin PQFP
MT90840AP
84 Pin PLCC
-40
°
C to 85
°
C
Figure 1 - Functional Block Diagram
MT90840
Distributed Hyperchannel Switch
Data Sheet
Output
Mux &
Drivers
PDo0
PDo7
2430 Position
TX Path
Connection Memory
Bidirectional
I/O
Driver
8
Serial
to
Parallel
&
Parallel
to
Serial
Conver-
ters
Bidirectional
I/O
Driver
STi7
STi0
STo7
STo0
4
CTo0-3
Timing
Control
Unit
PDi0
PDi7
PCKR
PCKT
RES
PPFRi
PPFTi/o
F0i/o
CPU Interface
Internal
Registers
TEST
Pins
5
8
8
S
C
C
I
R
A
V
V
Multiple Pages of 512 Position
TX Path Data Memory
8
512 Position
RX Path
Connection Memory
8
Multiple Pages of 2430-Byte
RX Path Data Memory
15
8
8
JTAG
16
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