- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359234 > MT9045 (Zarlink Semiconductor Inc.) T1/E1/OC3 System Synchronizer PDF資料下載
參數(shù)資料
| 型號： | MT9045 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | T1/E1/OC3 System Synchronizer |
| 中文描述： | T1/E1/OC3系統(tǒng)同步 |
| 文件頁數(shù)： | 8/34頁 |
| 文件大?。?/td> | 495K |
| 代理商： | MT9045 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁
MT9045
Data Sheet
8
Zarlink Semiconductor Inc.
Output Interface Circuit
The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in Figure
5. The Output Interface Circuit uses four Tapped Delay Lines followed by a T1 Divider Circuit, an E1 Divider Circuit,
and a DS2 Divider Circuit to generate the required output signals.
Four tapped delay lines are used to generate 16.384MHz, 12.352MHz, 12.624MHz and 19.44 MHz signals.
The E1 Divider Circuit uses the 16.384MHz signal to generate four clock outputs and three frame pulse outputs.
The C8o, C4o and C2o clocks are generated by simply dividing the C16o clock by two, four and eight respectively.
These outputs have a nominal 50% duty cycle.
The T1 Divider Circuit uses the 12.384MHz signal to generate the C1.5o clock by dividing the internal C12 clock
by eight. This output has a nominal 50% duty cycle.
The DS2 Divider Circuit uses the 12.624 MHz signal to generate the clock output C6o. This output has a nominal
50% duty cycle.
Figure 5 - Output Interface Circuit Block Diagram
The frame pulse outputs (F0o, F8o, F16o, TSP, and RSP) are generated directly from the C16 clock.
The T1 and E1 signals are generated from a common DPLL signal. Consequently, all frame pulse and clock outputs
are locked to one another for all operating states, and are also locked to the selected input reference in Normal
Mode. See Figures 14 & 16.
All frame pulse and clock outputs have limited driving capability, and should be buffered when driving high
capacitance (e.g., 30pF) loads.
Tapped
Delay
Line
From
DPLL
T1 Divider
E1 Divider
16MHz
12MHz
C1.5o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
Tapped
Delay
Line
Tapped
Delay
Line
Tapped
Delay
Line
DS2 Divider
12MHz
19MHz
C6o
C19o
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9045AN | T1/E1/OC3 System Synchronizer |
| MT9046 | T1/E1 System Synchronizer with Holdover |
| MT9046AN | T1/E1 System Synchronizer with Holdover |
| MT90503 | 2048VC AAL1 SAR |
| MT90503AG | CLIP, STRAIN RELIEF, 50WAY; For use with:820 Series Tripolarized Wiremount Sockets; Ways, No. of:50; Material:Metal; Connector type:Strain Relief RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9045AN | 制造商:Microsemi Corporation 功能描述: |
| MT9045AN1 | 制造商:Microsemi Corporation 功能描述:FRAMER E1/OC3/T1 3.3V 48SSOP - Rail/Tube 制造商:Microsemi Corporation 功能描述:T1/E1/OC3 SYSTEM SYNCHRONIZER |
| MT9045ANR1 | 制造商:Microsemi Corporation 功能描述:FRAMER E1/OC3/T1 3.3V 48SSOP - Tape and Reel 制造商:Microsemi Corporation 功能描述:iB FREE T1/E1/OC3 SYSTEM SYNCHRONIZER 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/OC3/T1 3.3V 48SSOP - Tape and Reel |
| MT9046 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL |
| MT9046AN | 制造商:Microsemi Corporation 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。