參數(shù)資料
型號: MT9045
廠商: Zarlink Semiconductor Inc.
英文描述: T1/E1/OC3 System Synchronizer
中文描述: T1/E1/OC3系統(tǒng)同步
文件頁數(shù): 18/34頁
文件大?。?/td> 495K
代理商: MT9045
MT9045
Data Sheet
18
Zarlink Semiconductor Inc.
The crystal should be a fundamental mode type - not an overtone. The fundamental mode crystal permits a simpler
oscillator circuit with no additional filter components and is less likely to generate spurious responses. The crystal
specification is as follows.
Frequency:
20MHz
Tolerance:
As required
Oscillation Mode:
Fundamental
Resonance Mode:
Parallel
Load Capacitance:
32pF
Maximum Series Resistance:35
Approximate Drive Level:
1mW
e.g., R1B23B32-20.0MHz
(20ppm absolute,
±
6ppm 0C to 50C, 32pF, 25
)
TIE Correction (using PCCi)
When Primary Holdover Mode is entered for short time periods, TIE correction should not be enabled. This will
prevent unwanted accumulated phase change between the input and output.
For instance, 10 Normal to Holdover to Normal mode change sequences occur, and in each case Holdover was
entered for 2s. Each mode change sequence could account for a phase change as large as 350ns. Thus, the
accumulated phase change could be as large as 3.5us, and, the overall MTIE could be as large as 3.5us.
0.05ppm is the accuracy of Holdover Mode
50ns is the maximum phase continuity of the MT9045 from Normal Mode to Holdover Mode
200ns is the maximum phase continuity of the MT9045 from Holdover Mode to Normal Mode (with or
without TIE Corrector Circuit)
When 10 Normal to Holdover to Normal mode change sequences occur without MTIE enabled, and in each case
holdover was entered for 2s, each mode change sequence could still account for a phase change as large as
350ns. However, there would be no accumulated phase change, since the input to output phase is re-aligned after
every Holdover to Normal state change. The overall MTIE would only be 350ns.
Reset Circuit
A simple power up reset circuit with about a 50us reset low time is shown in Figure 10. Resistor R
P
is for protection
only and limits current into the RST pin during power down conditions. The reset low time is not critical but should
be greater than 300ns.
Phasehold
Phasestate
Phase10
0.05ppm
2s
×
100ns
=
=
50ns
200ns
250ns
=
+
=
10
250ns
100ns
+
(
)
×
3.5us
=
=
相關PDF資料
PDF描述
MT9045AN T1/E1/OC3 System Synchronizer
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