參數(shù)資料
型號: MT9043
廠商: Zarlink Semiconductor Inc.
英文描述: T1/E1 System Synchronizer
中文描述: T1/E1的系統(tǒng)同步
文件頁數(shù): 13/29頁
文件大小: 453K
代理商: MT9043
MT9043
Data Sheet
13
Zarlink Semiconductor Inc.
5. TBR 4 November 1995
6. TBR 12 December 1993
7. TBR 13 January 1996
8. ITU-T I.431 March 1993
Applications
This section contains MT9043 application specific details for clock and crystal operation, reset operation, power
supply de coupling, and control operation.
Master Clock
The MT9043 can use either a clock or crystal as the master timing source.
In Freerun Mode, the frequency tolerance at the clock outputs is identical to the frequency tolerance of the source
at the OSCi pin. For applications not requiring an accurate Freerun Mode, tolerance of the master timing source
may be
±
100ppm. For applications requiring an accurate Freerun Mode, such as AT&T TR62411, the tolerance of
the master timing source must be no greater than
±
32ppm.
Another consideration in determining the accuracy of the master timing source is the desired capture range. The
sum of the accuracy of the master timing source and the capture range of the MT9043 will always equal 230ppm.
For example, if the master timing source is 100ppm, then the capture range will be 130ppm.
Clock Oscillator
- when selecting a Clock Oscillator, numerous parameters must be considered. This includes
absolute frequency, frequency change over temperature, output rise and fall times, output levels and duty cycle.
Figure 8 - Clock Oscillator Circuit
For applications requiring
±
32ppm clock accuracy, the following clock oscillator module may be used.
FOX F7C-2E3-20.0MHz
Frequency:
Tolerance:
Rise & Fall Time:
Duty Cycle:
20MHz
25ppm 0C to 70C
10ns (0.33V 2.97V 15pF)
40% to 60%
CTS CB3LV-5I-20.0 MHz
Frequency:
Tolerance:
Rise & Fall Time:
Duty Cycle:
20MHz
25ppm
10ns
45% to 55%
+3.3V
20MHz OUT
GND
0.1uF
+3.3V
OSCo
MT9043
OSCi
No Connection
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