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參數(shù)資料
| 型號： | MT8940 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | ISO-CMOS ST-BUS⑩ FAMILY T1/CEPT Digital Trunk PLL |
| 中文描述： | 異意法半導體的CMOS總線⑩家庭T1/CEPT數(shù)字集群鎖相環(huán) |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 299K |
| 代理商： | MT8940 |
ISO-CMOS
MT8940
3-29
10
C8Kb
Clock 8 kHz- Bidirectional (TTL compatible input and open drain output with 100K
internal resistor to V
DD
)
- This is the 8 kHz input signal on the rising edge of which DPLL #2
locks during its NORMAL mode. When DPLL #2 is in SINGLE CLOCK mode, this pin outputs
an 8 kHz signal provided by DPLL #1, which is also connected internally to DPLL #2.
11
C4o
Clock 4.096 MHz (Three state output) -
This is the inverse of the signal appearing on pin
13 (C4b) at 4.096 MHz and has a rising edge in the frame pulse (F0b) window. The high
impedance state of this output is controlled by EN
C4o
(pin 9).
Ground (0 Volt)
12
V
SS
C4b
13
Clock 4.096 MHz- Bidirectional (TTL compatible input and Totem-pole output)
- When
the mode select bit MS3 (pin 17) is HIGH, it provides the 4.096 MHz clock output with the
falling edge in the frame pulse (F0b) window. When pin 17 is LOW, C4b is an input (pulled
internally to V
DD
) to an external clock at 4.096 MHz.
Clock 2.048 MHz (Three state output)
- This is the divide by two output of C4b (pin 13) and
has a falling edge in the frame pulse (F0b) window. The high impedance state of this output
is controlled by EN
C2o
(pin 16).
Clock 2.048 MHz (Three state output) -
This is the divide by two output of C4b (pin 13) and
has a rising edge in the frame pulse (F0b) window. The high impedance state of this output is
controlled by EN
C2o
(pin 16).
Enable 2.048 MHz clock (TTL compatible input)
- This active high input (pulled internally
to V
DD
) enables both C2o and C2o outputs (pins 14 and 15). When LOW, these outputs are
in high impedance condition.
14
C2o
15
C2o
16
EN
C2o
17
MS3
Mode select 3 input (TTL compatible) -
This input (pulled internally to V
DD
) in conjunction
with MS2 (pin 7) selects the minor mode of operation for DPLL #2. (Refer to Table 3.)
18,19
Ai, Bi
Inputs A and B (TTL compatible) -
These are the two inputs (pulled internally to V
SS
) of the
uncommitted NAND gate
.
20
Y
o
CVb
Output Y (Totem pole output) -
Output of the uncommitted NAND gate.
21
Variable clock Bidirectional (TTL compatible input and Totem-pole output) -
When
acting as an output (MS1-LOW) during the NORMAL mode of DPLL #1, this pin provides the
1.544 MHz clock locked to the input frame pulse F0i (pin 5). When MS1 is HIGH, it is an
input (pulled internally to V
DD
) to an external clock at 1.544 MHz or 2.048 MHz to provide the
internal signal at 8 kHz to DPLL #2.
22
CV
Variable clock (Three state output) -
This is the inverse output of the signal appearing on
pin 21, the high impedance state of which is controlled EN
CV
(pin 1).
Reset (Schmitt trigger input) -
This input (active LOW) evokes reset condition for the
device.
23
RST
24
V
DD
V
DD
(+5V)
Power supply.
Pin Description (continued)
Pin #
Name
Description
相關PDF資料 |
PDF描述 |
|---|---|
| MT8940-1 | ISO-CMOS ST-BUS⑩ FAMILY T1/CEPT Digital Trunk PLL |
| MT8940AC | T1/CEPT Digital Trunk PLL |
| MT8940AE | ISO-CMOS ST-BUS⑩ FAMILY T1/CEPT Digital Trunk PLL |
| MT8941B | Advanced T1/CEPT Digital Trunk PLL(先進的T1/CEPT數(shù)字中繼鎖相環(huán)) |
| MT8941B | CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT8940-1 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY T1/CEPT Digital Trunk PLL |
| MT8940AC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:T1/CEPT Digital Trunk PLL |
| MT8940AE | 制造商:MITEL 功能描述: |
| MT8941 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Advanced T1/CEPT Digital Trunk PLL |
| MT8941AE | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
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