參數(shù)資料
型號(hào)： MT8931C
廠(chǎng)商： Mitel Networks Corporation
英文描述： Subscriber Network Interface Circuit(用戶(hù)網(wǎng)絡(luò)接口電路（提供點(diǎn)到點(diǎn)或點(diǎn)到多點(diǎn)數(shù)字傳送）)
中文描述： 用戶(hù)網(wǎng)絡(luò)接口電路（用戶(hù)網(wǎng)絡(luò)接口電路（提供點(diǎn)到點(diǎn)或點(diǎn)到多點(diǎn)數(shù)字傳送））
文件頁(yè)數(shù)： 14/40頁(yè)
文件大小： 309K
代理商： MT8931C
MT8931C
9-84
ii) Data
The data field refers to the Address, Control and
Information
fields
defined
recommendations. A valid frame should have a data
field of at least 16 bits. The first and second byte in
the data field is the address of the frame.
in
the
CCITT
iii) Frame Check Sequence (FCS)
The 16 bits following the data field are the frame
check sequence bits. The generator polynomial is:
G(x)=x
16
+x
12
+x
5
+1
The transmitter calculates the FCS on all bits of the
data field and transmits the complement of the FCS
with most significant bit first. The receiver performs
a similar computation on all bits of the received data
but also includes the FCS field. The generating
polynomial will assure that if the integrity of of the
transmitted data was maintained, the remainder will
have a consistent pattern and this can be used to
identify, with high probability, any bit errors occurred
during transmission. The error status of the received
packet is indicated by B7 and B6 bits in the HDLC
Status Register.
iv) Zero Insertion and Deletion
The transmitter, while sending either data from the
FIFO or the 16 bits FCS, checks the transmission on
a bit-by-bit basis and inserts a ZERO after every
sequence of five contiguous ONEs (including the last
five bits of FCS) to ensure that the flag sequence is
not imitated. Similarly the receiver examines the
incoming frame content and discards any ZERO
directly following the five contiguous ONEs.
v) Abort
The transmitter aborts a frame by sending a zero
followed by seven consecutive ONEs. The FA bit in
the HDLC Control Register 2 along with a write to the
HDLC Transmit FIFO enables the transmission of an
abort sequence instead of the byte written to the
register (to have a valid abort there must be at least
two bytes in the packet). On the receive side, a
frame abort is defined as seven or more contiguous
ONEs occurring after the start flag and before the
end flag of a packet. An interrupt can be generated
on reception of the abort sequence using FA bit in
the HDLC Interrupt Mask/Vector Registers (refer to
Tables 9 and 10).
Interframe Time Fill
When the HDLC Tranceiver is not sending packets,
the transmitter can be in one of two states mentioned
below depending on the status of the IFTF bit in the
HDLC Control Register 1.
i) Idle State
The Idle state is defined as 15 or more contiguous
ONEs. When the HDLC Protocoller is observing this
condition on the receiving channel, the Idle bit in the
HDLC Status Register is set HIGH. On the transmit
side, the Protocoller ends the transmission of all
ones (idle state) when data is loaded into the
transmit FIFO.
CCITT I.430 Specification requires every TE that
does not have layer 2 frames to transmit, to send
binary ONEs on the D-channel. In this manner, other
TEs on the line will have the opportunity to access
the D-channel using the priority mechanism circuitry.
ii) Flag Fill State
The HDLC Protocoller transmits continuous flags
(7E
Hex
) in Interframe Time Fill state and ends this
state when data is loaded into the transmit FIFO.
The reception of the interframe time fill will have the
effect of setting the idle bit in the HDLC Status
Register is set to ’0’.
HDLC Transmitter
On power up, the HDLC transmitter is disabled and
in the idle state. The transmitter is enabled by
setting the TxEN bit in the HDLC Control Register 1.
To start a packet, the data is written into the 19 byte
Transmit FIFO starting with the address field. All the
data must be written to the FIFO in a bytewide
manner. When the data is detected in the transmit
FIFO, the HDLC protocoller will proceed in one of the
following ways:
1)
If the transmitter is in idle state, the present byte
of ones is completely transmitted before sending
the opening flag. The data in the transmit FIFO
is then transmitted. A TE transmitting on the D-
channel will use the contention circuitry
described previously in
Mechanism to access this channel.
D-channel Priority
2)
If the transmitter is in the flag fill state, the
flag presently being transmitted is used as the
opening flag for the packet stored in the transmit
FIFO.
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