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| 型號： | MT8931B |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | () |
| 中文描述： | （） |
| 文件頁數(shù)： | 22/29頁 |
| 文件大?。?/td> | 277K |
| 代理商： | MT8931B |
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MSAN-141
Application Note
A-222
Breakdown Voltage
DC Forward Current
Reverse Recovery Time
Peak Forward Surge Current
Pulse Width = 1 s
Pulse Width = 1
μ
s
75 V
300 mA
4 ns
1 A
4 A
However, to provide extra protection when the power
fault conditions may exceed that of I.430 or when the
interface wiring is exposed, gaz tubes can be used
on the four-wire interface side. Gas tubes have very
low capacitance (usually 1pF) and will not affect the
performance of the device regarding pulse and
impedance templates.
8.0
HDLC FORMATTER
The HDLC formatter incorporated on the SNIC
handles the bit oriented protocol as per level 2 of the
X.25 packet switching protocol defined by CCITT. In
the ISDN environment, this Packet Assembly and
Disassembly (PAD) function is fundamental to the
structuring of the D-channel as per the LAPD
signalling protocol, which will be the full layer two
protocol used to route the voice and data channels
through the ISDN network.
8.1
Packet Structure
By performing the PAD function the HDLC formatter
will structure the packet as shown in Table 7. This
implies that the HDLC formatter will automatically
insert the opening and closing flags, it will assure
data transparency by inserting and deleting a zero
after five consecutive ones (in order to avoid
duplicating the flag sequence). It will also generate
and compare the cyclical redundancy check
calculated for each packet using the generating
polynomial: G(X)=X
16
+X
12
+X
5
+1.
Table 7. Frame Format
The HDLC formatter can only be accessed through
the microprocessor port in the form of internal
registers or FIFOs. Asynchronous registers provide
full control of all features as well as providing device
status information. This structure consists of the
following. On power up, the HDLC Control Register 1
must be initialized according to the specific
application. This includes disabling the HDLC
transmitter and receiver, enabling the address
recognition (if desired), selecting the relevant port for
both the receiver and transmitter, selecting the
desired interframe time fill
1,
and disabling the HDLC
loopback. The user can then select the desired
sources of interrupts using the HDLC Interrupt Mask
Register and/or Master Control Register. (It is also a
good practice to reset the receive and transmit
FIFOs before beginning a communication session in
the event that unwanted data has made its way into
the FIFOs during the power up sequence.)
After the initialization process, the HDLC formatter
can be used to transfer packetized D-channel over
either serial port (i.e., S-Bus or ST-BUS). Structuring
the packet is accomplished by building the message
in the 19 byte deep TxFIFO using the relevant tags to
identify the end of or an aborted packet. (Tagging a
byte is achieved by setting the appropriate bit in the
HDLC Control Register 2 then writing to the Tx
FIFO.) If the packet exceeds 19 bytes, the transmitter
must be enabled to deplete the FIFO before writing
any further information to the packet. An algorithm
for building a valid packet is provided in Figure 27.
If the transmission of the packet is directed to the S-
Bus port in the TE mode and the HDLC transmitter is
enabled, the SNIC will activate the priority
mechanism circuitry to request the D channel as
soon as data is written to the Tx FIFO. Once the D-
channel acknowledgment signal is received the
packet will be transmitted immediately following the
opening
flag.
If
a
collision
transmission, the remainder of the packet will be
depleted from the Tx FIFO but will not be sent on to
the D-channel of the S-Bus. Therefore, this packet
must be reloaded into the Tx FIFO. When the SNIC
is in NT mode or the packetized D-channel is
directed to the ST-BUS port, the packet will be
transmitted as soon as the transmitter is enabled.
occurs
during
During the reception of a packet, the 16 kbit/s D-
channel is examined on a bit-by-bit basis with all
inserted zeros removed, the CRC calculated and the
bits organized into 8 bit bytes in the 19 deep RxFIFO.
The control characters surrounding the packet
structure such as the flags and the abort sequence
will never make their way into the RxFIFO. If address
recognition is enabled, the address field (one or two
bytes) is compared to the byte in the Receive
Address Registers. If a match does not occur, the
received packet will be ignored and will not be
loaded into the receive FIFO. Once an address
match occurs, the packet, starting with the address
field will be loaded into the RxFIFO for further
processing.
FLAG
DATA FIELD
FCS
FLAG
One Byte
n
B
ytes (n
≥
2)
Two Bytes
One Byte
1
It must be noted that if the flag fill mode is enabled with the transmitter disabled, the HDLC formatter will not generate the opening
flag once the transmitter is enabled. This will result in the first packet being lost.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT8931BC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Subscriber Network Interface Circuit |
| MT8931BE | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Subscriber Network Interface Circuit |
| MT8931BP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Subscriber Network Interface Circuit |
| MT8931C | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Subscriber Network Interface Circuit |
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