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參數(shù)資料
| 型號： | MT8926AP |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | ISO-CMOS ST-BUS⑩ FAMILY T1 Performance Monitoring Adjunct Circuit (PMAC) |
| 中文描述： | 異意法半導體的CMOS總線⑩家庭T1性能監(jiān)控兼任電路（PMAC下） |
| 文件頁數(shù)： | 13/26頁 |
| 文件大?。?/td> | 309K |
| 代理商： | MT8926AP |
4-15
MT8926
Table 14. PMAC Control Word (CSTi1 Channel 11)
Bit
Name
Description
7
SER
SE Counter Reset. Toggling this bit from high to low will reset the severely errored
framing event counter (SE counter, CSTo channel 19 bits 7-4) and event indicator
(SEI bit, CSTo channel 31 bit 4).
6
FER
FE Counter Reset. Toggling this bit from high to low will reset the framing error
counter (FE counter, CSTo channel 19 bits 3-0) and saturation indicator (FEI bit,
CSTo channel 31 bit 3).
5
CRCR
CRC Counter Reset. Toggling this bit from high to low will reset the eight bit CRC
error counter (CRC, CSTo channel 11) and saturation indicator (CSI bit, CSTo
channel 31 bit 2)
4
BPVR
BPV Counter Reset. Toggling this bit from high to low will reset the eight bit BPV
counter (BPV, CSTo channel 23) and saturation indicator (BSI bit, CSTo channel 31
bit 1).
3
FSel
Framing Pattern Select. With FSel = 1 and an SF signal detected, both F
S
and F
T
errors are considered by the FE and SE counters. The user must set this bit high in
ESF mode.
With FSel = 0 and an SF signal detected, only errors in F
T
bits are considered by the
FE and SE counters.
2
8KEn
8 KHz Output Enabled. When 8KEn = 1, the E8Ko output will be enabled. That is, the
signal input at E8Ki will be output on E8Ko. See Figure 12 for timing.
When 8KEn = 0, the E8Ko output will be high.
1
INTA
Interrupt Acknowledge. When INTA = 1 the MT8926 interrupts are armed or have
been triggered (see Table 15). Once INTA is set all interrupting signals of a group
must be inactive before another interrupt of that group can assert the IRQ output
(active low). See Pin Description, pin 20.
When this bit is low the IRQ output state will be high impedance. IRQ will remain in
this state as long as INTA remains low or there are no interrupting events (Tables 16
and 17).
0
FDLEn
Facility Data Link Enable. FDLEn = 1 enables transmission of the facility data link bit-
oriented messages on FDLo. The BOM byte is stored in the TxBOM register (Table
13, CSTi1 Channel 7). See Figure 7 for illustration.
When FDLEn = 0, the data received on FDLi is multiplexed back out of the MT8926
on FDLo. See Figure 19 for timing.
MT8926 to the TxFDL input of the MT8976/77. The
1SEC output pin or the two second TMR bit of the
Miscellaneous Status Word (CSTo channel 7 bit 0)
are derived from the ST-BUS timing and can be used
to initiate the transmission of these messages.
When the MT8926 is synchronized to an SF T1
signal, its receive FDL functions are disabled. BOMV
of the PMAC Miscellaneous Status Register and RAI
of Master Status Word 1 will be zero.
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