參數(shù)資料
型號(hào)： MT8926AE
廠商： Mitel Networks Corporation
英文描述： ISO-CMOS ST-BUS⑩ FAMILY T1 Performance Monitoring Adjunct Circuit (PMAC)
中文描述： 異意法半導(dǎo)體的CMOS總線⑩家庭T1性能監(jiān)控兼任電路（PMAC下）
文件頁(yè)數(shù)： 15/26頁(yè)
文件大小： 309K
代理商： MT8926AE
4-17
MT8926
In slave or loop-timed operation 8KEn of the PMAC
Control Word (Table 14, CSTi1 channel 11 bit 2) will
be high, which will pass the signal on E8Ki through
to E8Ko. In Master mode or if loop-timing is acquired
from another interface, 8KEn must be low, which will
make E8Ko high.
Interrupts
The MT8926 interrupts originate from eight sources,
which are divided into two groups. Group one (G1)
contains ALRM (SF Yellow Alarm), RAI (ESF Yellow
Alarm), SLIP and SYN - all except SLIP must be
cleared by some means external to the MT8926.
Group two (G2) contains SEI, FSI, CSI, and BSI -
these can be cleared via the MT8926. See Tables 16
and 17 for further information.
The interrupting mechanism is controlled by the
interrupt acknowledge bit (INTA) of the PMAC control
word (Table 14). The status of the interrupts is output
on IRQ. This will allow the three valid states
described in Table 15.
.
Table 15. Interrupt States
In the Cleared state (INTA = 0) interrupt sources are
ignored and IRQ will always be high impedance. If
the interrupts are not being used, then INTA should
remain in the Cleared state. When the MT8926 is in
the Armed state and an interrupt occurs, it will go to
the Triggered state (IRQ = 0).
State
Cleared
Armed
Triggered
INTA Bit
0
1
1
IRQ Output
High Impedance
High Impedance
0
When a G1 interrupt occurs and IRQ goes low
(Triggered), no other G1 or G2 interrupts will affect
IRQ. If IRQ is then Cleared and re-Armed, only an
active G2 interrupt can Trigger IRQ low unless the
G1 interrupt has been removed. That is, both the
MT8926 interrupt mechanism and the interrupting
source of a group must be cleared before a further
interrupt of that group can cause IRQ to go low. The
only exception to this is SEI, which can be cleared by
INTA ( see Table 11).
A PMAC interrupting signal is either a low-to-high
transition or a change in state (SLIP), therefore, for
IRQ to go low the MT8926 must be Armed before the
initiating edge occurs. In the case where all
interrupts are quiescent and then an interrupt
becomes active, while the MT8926 is in its Clear
state, IRQ will remain in a high impedance condition.
This is true even if the MT8926 is then put in the
Armed state and the interrupt persists (see Figure 8).
It should be noted that when an SF mode T1 signal is
being received the MT8926 CRC error counter will
be incremented once every two superframes (24
frames or 3 msec.). This is because SF mode T1 has
no CRC bits. Therefore, the CRC circuitry of the
MT8976/77 will compare the calculated CRC
remainder with the received FS bits, which will result
in a mismatch. This will increment the MT8976/77
and MT8926 CRC error counters.
The MT8926 CRC error counter will count to 255 and
then overflow to zero, which will cause an interrupt
(IRQ). Therefore, when an SF mode T1 signal is
being received an interrupt will be asserted every
256 X 3 msec. = 768 msec. This can be avoided by
clearing the CRC error counter before it overflows. A
change of state of the 1SEC output (once every 0.5
seconds) can be used to trigger a high-to-low
G1 interrupts are cleared when SYN, ALRM, and RAI = 0.
The SYN interrupt indicates that a LOS or a AIS condition may exist.
Note: AND denotes a logical and.
Table 16. Group One (G1) Interrupt Activation and Clearing
Signal
To Trigger interrupt (IRQ low)
To Clear and Arm interrupt
(
IRQ high
impedance)
ALRM
ALRM bit low to high AND other G1 interrupts
quiescent AND IRQ high impedance.
RAI bit low to high AND other G1 interrupts
quiescent and IRQ high impedance.
CSTi0/CSTo Channel 15 Bit 1 (SLIP) changes state
AND other G1 interrupts quiescent AND IRQ high
impedance.
CSTi0/CSTo Channel 15 Bit 0 (SYN) low to high
AND other G1 interrupts inactive AND IRQ high
impedance.
The INTA bit of the PMAC Control Word
(CSTi1 channel 11 bit 1) should be made
low to clear the interrupt mechanism (IRQ
high impedance). All G1 interrupts must be
quiescent and then INTA must be made
high before a further interrupt can be
generated from G1.
See MT8976/77 data sheet master status
word 1 for information on the SLIP and
SYN bits.
RAI
SLIP
SYN
相關(guān)PDF資料
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MT8926AP ISO-CMOS ST-BUS⑩ FAMILY T1 Performance Monitoring Adjunct Circuit (PMAC)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT8926AP 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY T1 Performance Monitoring Adjunct Circuit (PMAC)
MT8930 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Subscriber Network Interface Circuit Preliminary Information
MT8930B 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:Subscriber Network Interface Circuit
MT8930BC 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:Subscriber Network Interface Circuit
MT8930BE 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:Subscriber Network Interface Circuit
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