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參數(shù)資料
| 型號(hào)： | MT8920B |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | ST-BUS Parallel Access Circuit(串行通信總線（ST-Bus）并行存取電路（在ST總線和并行系統(tǒng)間提供一個(gè)簡(jiǎn)單接口）) |
| 中文描述： | 意法半導(dǎo)體總線并行訪問電路（串行通信總線（圣總線）并行存取電路（在圣總線和并行系統(tǒng)間提供一個(gè)簡(jiǎn)單接口）） |
| 文件頁(yè)數(shù)： | 9/29頁(yè) |
| 文件大?。?/td> | 215K |
| 代理商： | MT8920B |
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CMOS
MT8920B
3-11
Figure 5 - Loopback Configurations
Interrupt Mask Register (1/2):
In static mode the
contents of this register masks bits in the Match Byte
Register that are ’don’t care’ bits
1 - bit masked
0 - bit not masked
In dynamic mode, each bit in this register and the
corresponding bit in the Match Byte Register define
what type of dynamic interrupt is selected. (Refer to
Table 5.)
Interrupt Flag Register (1/2):
In static mode
the least significant bit in this register is set to 1 to
flag the corresponding path in which the interrupt
occurs.
In dynamic mode this register sets the bits which
reflect the position of the bits in the corresponding
Interrupt Register which caused the interrupt.
Figure 6 - STo1 Configurations
Interrupt Vector Register
This register shown in Figure 7 is common to both
interrupt paths and stores an 8 bit vector number
which will be output on the data bus when
Interrupt Acknowledge (IACK) is asserted. Bits
labelled V
2
- V
7
are stored by the controlling
μ
P.
Bits IRQ1 and IRQ2 are set by the STPA to indicate
which path caused the interrupt. This creates unique
vectors which are used by the
μ
P to vector to
interrupt service routines. This feature may be
bypassed by simply not asserting IACK during
interrupt acknowledged.
Figure 7 - Interrupt Vector Registers
STo0
STi0
Rx0
μ
P
Control Register 2
Bits D
1
= 0, D
0
= 1
a)
STo0
STi0
Tx0
Rx0
μ
P
Control Register 2
Bits D
1
= 1, D
0
= 0
b)
STo0
STi0
Control Register 2
Bits D
1
= 1, D
0
= 1
μ
P
Tx0
Rx0
c)
D7
D6
D5
D4
D3
D2
D1
D0
V
7
V
6
V
5
V
4
V
3
V
2
IRQ2
IRQ1
STo0
STi0
STo1
STo0
STi0
STo1
STo0
STi0
STo1
μ
P
μ
P
μ
P
Tx0
Rx0
Tx1
1 Frame Delay
Tx0
Rx0
Tx1
Tx0
Rx0
Tx1
1 Frame Delay
Control Register 2
Bits D
3
= 0, D
2
= 1
Control Register 2
Bits D
3
= 1, D
2
= 0
Control Register 2
Bits D
3
= 1, D
2
= 1
a)
b)
c)
相關(guān)PDF資料 |
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| MT8924-1 | PCM Conference Circuit (PCC) Preliminary Information |
| MT8924AE | PCM Conference Circuit (PCC) Preliminary Information |
| MT8924AS | PCM Conference Circuit (PCC) Preliminary Information |
| MT8924 | PCM Conference Circuit (PCC) Preliminary Information |
| MT8930B | () |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8920B-1 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
| MT8920BC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
| MT8920BE | 制造商:Mitel Networks Corporation 功能描述:COMMUNICATIONS INTERFACE, 28 Pin, Plastic, DIP |
| MT8920BE1 | 制造商:Zarlink Semiconductor Inc 功能描述:ST-BUS PARALLEL ACCESS CIRCUIT 28PDIP - Rail/Tube 制造商:Microsemi 功能描述:Microsemi MT8920BE1 Interface Misc |
| MT8920BP | 制造商:Microsemi Corporation 功能描述: 制造商:MITEL 功能描述: |
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