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參數(shù)資料
| 型號： | MT8910-1AP |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | CMOS ST-BUS⑩ FAMILY Digital Subscriber Line Interface Circuit |
| 中文描述： | 意法半導(dǎo)體的CMOS總線⑩家庭數(shù)字用戶線接口電路 |
| 文件頁數(shù)： | 23/26頁 |
| 文件大?。?/td> | 419K |
| 代理商： | MT8910-1AP |
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Preliminary Information
MT8910-1
9-25
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
(
1
) except OSC2
Note
1)
This is a specification on the maximum parallel capacitance to AC ground, connected directly to the pins. Higher
capacitance is acceptable when placed in series with resistor networks such as the line termination impedance.
2)
Not production tested.
Figure 15 - External Clock Timing in LT Mode
Timing is over recommended temperature & power supply voltages.
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Notes:
1)
External clock tolerance of ±5 ppm in LT mode or ±50 ppm in NT mode is required.
2)
Absolute jitter on OSC2 must be less than 2.0ns RMS in order to maximize performance.
3)
In LT mode the C4b and OSC2 clocks must be externally frequency locked (i.e., f
OSC2
= 2.5 x f
C4b
). The relative phase
between the clocks is not critical.
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
8
O
U
T
P
U
T
S
V
Bias
Voltage
V
Bias
0.5AV
DD
V
Relative to AV
SS
C
L
=1 μF minimum to AV
SS
Relative to V
Bias
C
L
= 1μF minimum to AV
SS
(see Note 2)
9
V
Ref
Voltage
V
Ref
-1.9
V
10
V
Bias
and/or V
Ref
load
Output High Voltage
(1)
Output Low Voltage
(1)
V
BL
V
OH
V
OL
V
OH
V
OL
1
M
11
2.4
V
I
OH
=10mA
I
OL
= 5.0mA
I
OH
=10μA
I
OL
=10μA
12
0.4
V
13
OSC2 Output High Voltage
3.5
V
14
OSC2 Output Low Voltage
1.5
V
15
Differential Output Voltage
(L
out+
to L
out-
)
Output Impedance
(L
out+
, L
out-
)
V
out
6.4
V
pp
R
L
=40
Measured by sourcing and
sinking 10 mA. Line Driver
active.
16
Z
out
0.5
17
Output Capacitance
(L
out+
, L
out-
)
High Impedance Leakage
C
o
I
OZ
I
DD
50
pF
(see Note 1)
18
10
μA
19
Supply Current
I
DD
65
10
mA
mA
Line Drivers active and
unloaded.
Low Power Mode
AC Electrical Characteristics
- External Clock Timing (Ref. Figure 15)
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
OSC2 Clock Frequency
1/t
MCF
t
OCH
/
t
MCF
t
OCT
t
JC
10.24
MHz
(see Notes 1, 2 & 3)
2
OSC2 Clock Duty Cycle
45
50
55
%
3
OSC2 Clock Transition Time
10
ns
4
C4b Jitter (wrt OSC2)
-15
+15
ns
(see Note 3)
DC Electrical Characteristics (continued)
- Voltages are with respect to ground (V
SS
) unless otherwise stated.
C4b
OSC2
V
IH
V
IL
V
IH
V
IL
t
JC
(See Note 3)
t
JC
t
OCH
t
OCT
t
OCT
t
MCF
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT8920 | ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
| MT8920B | ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
| MT8920B-1 | ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
| MT8920BC | ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
| MT8920BE | ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8920 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
| MT8920AE | 制造商:Mitel Networks Corporation 功能描述: |
| MT8920B | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
| MT8920B-1 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
| MT8920BC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
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