參數(shù)資料
型號(hào): MT8910-1AP
廠商: Mitel Networks Corporation
英文描述: CMOS ST-BUS⑩ FAMILY Digital Subscriber Line Interface Circuit
中文描述: 意法半導(dǎo)體的CMOS總線⑩家庭數(shù)字用戶線接口電路
文件頁(yè)數(shù): 2/26頁(yè)
文件大?。?/td> 419K
代理商: MT8910-1AP
MT8910-1
Preliminary Information
9-4
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
DIP PLCC
1
1
L
out-
Line Out Minus.
One of a pair of differential analog outputs for the 80 kbaud/s 2B1Q
signal, biased at V
Bias
.
Line Out Plus.
One of a pair of differential analog outputs for the 80 kbaud/s 2B1Q signal,
biased at V
Bias
.
Analog Ground.
Tie to V
SS
.
I/O Structure Test Input.
When TSTen is high, TSTin is used as a source to all output
drivers. Refer to “I/O Structure Test" in functional description for more details. Tie to V
SS
for normal operation.
2
3
L
out+
3
5
AV
SS
TSTin
4
6
5
8
CDSTi
Control/Data ST-BUS Input.
A 2048 kbit/s serial PCM/data input for the D- and
C-channels in Dual mode. Unused in Single mode and should be connected to V
SS
.
Data ST-BUS Input.
A 2048 kbit/s serial PCM/data input for the D-, C-, B1- and B2-
channels in Single mode. In Dual mode, only the B-channels are input.
6
12
DSTi
7
13
V
SS
DSTo
Ground.
8
14
Data ST-BUS Output.
A 2048 kbit/s serial PCM/data output for the D-, C-, B1- and B2-
channels in Single mode. In Dual mode, only the B-channels are output. This output is
placed in high impedance during the unused channel times.
9
15
CDSTo
Control/Data ST-BUS Output.
A 2048 kbit/s serial PCM/data output for the D- and
C- channels in Dual mode. It is placed in high impedance in Single mode, and during the
unused channel times in Dual mode.
10
16
F0od
Delayed Frame Pulse Output.
A 244 ns wide negative going pulse indicating the end of
the active ST-BUS channel times of the device to allow for daisy-chaining of other ST-BUS
devices. Active after channel 0 in Dual Port mode and Channel 3 in Single Port Mode.
11
18
TSTout
I/O Structure Test Output.
When TSTen is high, the TSTout provides the output of an
XOR chain which is sourced from all digital inputs. Refer to “I/O Structure Test" in
functional description for more details. Leave unconnected for normal operation.
12
19
MS0
Mode Select 0.
CMOS input. Refer to Table 1.
13
20
MS1
Mode Select 1.
CMOS input. Refer to Table 1.
44 PIN PLCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
28
27
26
25
24
23
22
21
Lout-
Lout+
AVSS
TSTin
CDSTi
DSTi
VSS
DSTo
CDSTo
F0od
TSTout
MS0
MS1
NT/LT
Lin+
Lin-
VRef
VBias
AVDD
IC
VDD
MRST
OSC1
OSC2
F0b
C4b
SFb
TSTen
28 PIN CERDIP
T
A
L
N
N
L
L
V
V
N
T
M
M
N
T
N
C
N
F
N
S
L
1
6 5 4 3 2
7
8
9
10
11
12
13
14
15
16
17
44 434241 40
39
38
37
36
35
34
33
32
31
30
29
23
1819 202122
24252627 28
NC
AVDD
NC
NC
NC
IC
VDD
MRST
OSC1
OSC2
NC
NC
CDSTi
NC
NC
NC
DSTi
VSS
DSTo
CDSTo
F0od
NC
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