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參數(shù)資料
| 型號： | MT8910-1AC |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | CMOS ST-BUS⑩ FAMILY Digital Subscriber Line Interface Circuit |
| 中文描述： | 意法半導(dǎo)體的CMOS總線⑩家庭數(shù)字用戶線接口電路 |
| 文件頁數(shù)： | 19/26頁 |
| 文件大?。?/td> | 419K |
| 代理商： | MT8910-1AC |
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Preliminary Information
MT8910-1
9-21
Figure 11 - Typical Connections for LT Mode (Single Port)
OSC1
OSC2
C4b
F0b
SFb
DSTi
DSTo
MS0
MS1
NT/LT
TSTin
TSTen
CDSTi
MRST
VSS
AVSS
VDD
AVDD
Lout+
Lin+
Lin-
Lout-
VBias
VRef
CDSTo
IC
TSTout
F0od
74HC04
10.24 MHz Clock
74HC04
4.096 MHz Clock
8 kHz Frame Pulse
12ms Superframe Pulse
PCM or Data In
PCM or Data Out
System Reset
20
19
17
18
16
6
8
12
13
14
4
15
5
21
7
3
22
24
2
28
27
1
25
26
9
23
11
10
V
DD
1
μ
F
0.1
μ
F
0.1
μ
F
1:1.3
1.5
μ
F
1.0
μ
F
1.0
μ
F
TO LINE FEED
SUPPLY
TO NEXT DSLIC
IN CHAIN
1
μ
F
MT8910-1
M
H
8
9
1
0
1
PLT
*Duty cycle: 45% to 55%
*
MRST, OSC1, C4b, F0b and SFb. TSTout=0 if all
input signals carry an even number of ones and
TSTout=1 if all input signals carry an odd number of
ones.
The I/O structure test also allows the verification of
the connection between the digital output pins and
the printed circuit board. After running the
initialization sequence, the I/O structure output test
can be enabled by setting the TSTen to a logic high
with the mode select pins MS0, MS1 and NT/LT set
to 1, 1, 0 respectively. This causes all digital outputs
to be driven from the I/O structure test input (TSTin)
pin1. The outputs affected include the DSTo,
CDSTo, F0od and TSTout
These same outputs can also be placed into a high
impedance state to allow the bed-of-nails tester or
some other in-circuit tester to drive a known signal or
pattern on any circuitry that may be connected to the
output pins of the MT8910-1. The high impedance
state is enabled by running the initialization pattern
described above then setting TSTen to a logic one
with the mode select pins MS0, MS1 and NT/LT set
to 1, 0, 0 respectively.
Note
1
:
Allow a propagation delay of approximately 800ns
from digital input to XOR output or TSTin to any
digital output.
Applications
The typical connection diagrams are shown in
Figures 11 and 12. In Figure 11, the MT8910-1
receives all its timing from the system including the
C4b, F0b and a frequency-locked 10.24 MHz master
clock. In Figure 12, the MT8910-1 is configured in
the NT mode which implies that all timing signals
including the F0b, C4b and SFb are being sourced
from the MT8910-1. These timing signal are
generated from an internal DPLL which divides a
10.24 MHz reference frequency down to a baseband
160 kHz. A comparison is performed on the
reference signal with the received line signal to
determine if the timing signals on the MT8910-1
have to be corrected.
The MT8910-1 is interfaced to the transmission line
through the Passive Line Termination network (PLT)
and transformer. The PLT provides the two to four
wire
conversion
and
compensation for the received signal. The whole
circuit is DC isolated from the line by the low
inductance transformer.
additional
frequency
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT8910-1AP | CMOS ST-BUS⑩ FAMILY Digital Subscriber Line Interface Circuit |
| MT8920 | ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
| MT8920B | ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
| MT8920B-1 | ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
| MT8920BC | ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8910-1AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Digital Subscriber Line Interface Circuit |
| MT8920 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
| MT8920AE | 制造商:Mitel Networks Corporation 功能描述: |
| MT8920B | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
| MT8920B-1 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit |
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