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    參數(shù)資料
    型號(hào): MT88L85
    廠商: Mitel Networks Corporation
    英文描述: 3V Integrated DTMFTransceiver with Power Down & Adaptive Micro Interface
    中文描述: 3V的集成DTMFTransceiver與掉電
    文件頁(yè)數(shù): 17/20頁(yè)
    文件大?。?/td> 350K
    代理商: MT88L85
    Advance Information
    MT88L85
    4-87
    Characteristics are over recommended operating conditions unless otherwise stated
    Typical figures are at 25°C, V
    DD
    =3V, and for design aid only: not guaranteed and not subject to production testing
    NOTES: 1)
    dBm=decibels above or below a reference power of 1 mW into a 600 ohm load.
    2)
    Digit sequence consists of all 16 DTMF tones.
    3)
    Tone duration=40 ms. Tone pause=40 ms.
    4)
    Nominal DTMF frequencies are used.
    5)
    Both tones in the composite signal have an equal amplitude.
    6)
    The tone pair is deviated by ± 1.5 %±2 Hz.
    7)
    Bandwidth limited (3 kHz) Gaussian noise.
    8)
    The precise dial tone frequencies are 350 and 440 Hz (±2 %).
    9)
    Guaranteed by design and characterization. Not subject to production testing.
    10)
    Referenced to the lowest amplitude tone in the DTMF signal.
    11)
    For guard time calculation purposes.
    Figure 15 - DS/RD/WR Clock Pulse
    AC Electrical Characteristics
    - MPU Interface
    - Voltages are with respect to ground (V
    SS
    ), unless otherwise stated.
    Characteristics
    Sym
    Min
    Typ
    Max
    Units
    Conditions
    1
    DS/RD/WR clock frequency
    f
    CYC
    t
    CYC
    t
    CL
    t
    CH
    t
    R,
    t
    F
    t
    RWS
    t
    RWH
    t
    AS
    t
    AH
    t
    DHR
    t
    DDR
    t
    DSW
    t
    DHW
    t
    CSS
    t
    CSH
    4.0
    MHz
    Figure 15
    2
    DS/RD/WR cycle period
    250
    ns
    Figure 15
    3
    DS/RD/WR low pulse width
    150
    ns
    Figure 15
    4
    DS/RD/WR high pulse width
    100
    ns
    Figure 15
    5
    DS/RD/WR rise and fall time
    20
    ns
    Figure 15
    6
    R/W setup time
    0
    ns
    Figures 16 & 17
    7
    R/W hold time
    26
    ns
    Figures 16 & 17
    8
    Address setup time (RS0)
    0
    ns
    Figures 16 - 19
    9
    Address hold time (RS0)
    26
    ns
    Figures 16 - 19
    10
    Data hold time (read)
    22
    ns
    Figures 16 - 19
    11
    DS/RD to valid data delay (read)
    80
    100
    ns
    Figures 16 - 19
    12
    Data setup time (write)
    35
    ns
    Figures 16 - 19
    13
    Data hold time (write)
    10
    ns
    Figures 16 - 19
    14
    Chip select setup time
    45
    ns
    Figures 16 - 19
    15
    Chip select hold time
    40
    ns
    Figures 16 - 19
    t
    CYC
    t
    R
    t
    CH
    t
    CL
    DS/RD/WR
    t
    F
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    參數(shù)描述
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