參數(shù)資料
型號: MT88E46
廠商: Mitel Networks Corporation
英文描述: Bellcore Compliant Calling Number Identification Circuit(兼容貝爾內(nèi)核主叫識別電路)
中文描述: 貝爾通訊兼容主叫號碼識別電路(兼容貝爾內(nèi)核主叫識別電路)
文件頁數(shù): 19/25頁
文件大?。?/td> 111K
代理商: MT88E46
19
Advance Information
MT88E46
Figure 13 - CAS Detection Timing
Figure 14 - FSK Data Interface Timing - Mode 0
Figure 15 - FSK Data Interface Timing - Mode 1
CAS
DET
(Output)
t
DET2
t
DW
= 416
μ
s nominal
t
DET1
See ‘AC Electrical Characteristics -
CAS Detection’ for t
DET1
and t
DET2
values.
Note: The relationship between DATA bit boundary and DCLK is symbolic only. In reality, the DATA bit boundary will jitter with
respect to the DCLK falling edges.
TIP/RING
DATA
(Output)
DCLK
(Output)
DR
(Output)
b7
b0 b1 b2 b3 b4 b5 b6 b7
b0 b1 b2 b3 b4 b5 b6 b7
b0 b1 b2 b3 b4 b5
b7
b0 b1 b2 b3 b4 b5 b6 b7
b0 b1 b2 b3 b4 b5 b6 b7
b0 b1 b2 b3
b6
stop
start
stop
start
stop
start
stop
start
stop
start
stop
start
t
IDD
t
CRD
t
RL
t
CL
t
CH
1/f
DCLK0
Demodulated Data
(Internal Signal)
DCLK (Data Clock)
(Schmitt Input)
DR (Data Ready)
(Output)
stop
start
stop
0
1
2
3
4
5
6
7
7
Word N
Word N+1
DATA
(Output)
5
Word N
Word N-1
1/f
DCLK1
t
RL
>t
DDH
The DCLK input must be low before and after DR falling edge.
Note 1: DCLK occurs during DR low and returns DR to high.
Note 2: DCLK occurs after DR, so DR is low for half a nominal bit time.
Note 3: When framing error (trailing stop bit a 0 instead of a 1) is not checked, the microcontroller only needs to send 8 DCLK
pulses to shift the byte out.
>t
DDS
4
3
2
1
0
6
7
stop
stop
7
0
Note 1
Note 2
Note 3
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參數(shù)描述
MT88E46_06 制造商:TI 制造商全稱:Texas Instruments 功能描述:Bellcore Compliant Calling Number Identification Circuit
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MT88E46AS1 制造商:Microsemi Corporation 功能描述:CALLER ID CMOS 3.58MHZ 3.3V/5V 20SOIC - Rail/Tube
MT88E46ASR 制造商:Microsemi Corporation 功能描述:CALLER ID CMOS 3.58MHZ 3.3V/5V 20SOIC - Tape and Reel
MT88E46ASR1 制造商:Microsemi Corporation 功能描述:CALLER ID CMOS 3.58MHZ 3.3V/5V 20SOIC - Tape and Reel