參數(shù)資料
型號: MT58L64L32D
廠商: Micron Technology, Inc.
英文描述: 64K x 32,3.3V I/O, Pipelined, Double-Cycle Deselect,SyncBurst SRAM(2Mb,3.3V輸入/輸出,流水線式,雙循環(huán)取消選擇,同步脈沖靜態(tài)RAM)
中文描述: 64K的x 32,3.3六/ O的流水線,雙循環(huán)取消,SyncBurst的SRAM(處理器,3.3V的輸入/輸出,流水線式,雙循環(huán)取消選擇,同步脈沖靜態(tài)內存)
文件頁數(shù): 6/24頁
文件大?。?/td> 432K
代理商: MT58L64L32D
6
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L128L18D_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, DCD SYNCBURST SRAM
TQFP PIN DESCRIPTIONS (continued)
x18
84
x32/x36
84
SYMBOL
ADSP#
TYPE
Input
DESCRIPTION
Synchronous Address Status Processor: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent
upon CE#, CE2, and CE2#. ADSP# is ignored if CE# is HIGH. Power-
down state is entered if CE2 is LOW or CE2# is HIGH.
Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
Mode: This input selects the burst sequence. A LOW on this pin
selects “l(fā)inear burst.” NC or HIGH on this pin selects “interleaved
burst.” Do not alter input state while device is operating.
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is DQa pins; Byte “b”
Output is DQb pins. For the x32 and x36 versions, Byte “a” is DQa pins;
Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is DQd pins.
Input data must meet setup and hold times around the rising edge
of CLK.
85
85
ADSC#
Input
31
31
MODE
Input
(a)
58, 59,
62, 63, 68, 69, 56-59, 62, 63
72, 73
(b)
8, 9, 12,
13, 18, 19,
22, 23
(a)
52, 53,
DQa
(b)
68, 69,
72-75, 78, 79
DQb
(c)
2, 3, 6-9,
12, 13
(d)
18, 19,
22-25, 28, 29
51
80
1
30
DQc
DQd
74
24
NC/
DQPa
NC/
DQPb
NC/
DQPc
NC/
DQPd
V
DD
NC/
I/O
No Connect/Parity Data I/Os: On the x32 version, these pins are No
Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte “b”
parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte
“b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.
Supply Power Supply: See DC Electrical Characteristics and Operating
Conditions for range.
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
Operating Conditions for range.
Supply Ground: GND.
14, 15, 41, 65, 14, 15, 41, 65,
91
4, 11, 20, 27,
54, 61, 70, 77 54, 61, 70, 77
5, 10, 17, 21,
26, 40, 55, 60, 26, 40, 55, 60,
67, 71, 76, 90 67, 71, 76, 90
38, 39, 42, 43 38, 39, 42, 43
91
4, 11, 20, 27,
V
DD
Q
5, 10, 17, 21,
V
SS
DNU
Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
No Connect: These signals are not internally connected and may be
connected to ground to improve package heat dissipation.
1-3, 6, 7, 16,
25, 28-30,
51-53, 56, 57,
66, 75, 78, 79,
95, 96
50
16, 66
NC
50
NC/
SA
No Connect: This pin is reserved for address expansion.
相關PDF資料
PDF描述
MT58L128L18F 128K x 18, Flow-Through SyncBurst SRAM(2Mb,流通式同步脈沖靜態(tài)RAM)
MT58L128V18F 128K x 18, Flow-Through SyncBurst SRAM(2Mb,流通式同步脈沖靜態(tài)RAM)
MT58L64L32F 64K x 32,Flow-Through SyncBurst SRAM(2Mb,流通式同步脈沖靜態(tài)RAM)
MT58L64L36F 64K x 36,Flow-Through SyncBurst SRAM(2Mb,流通式同步脈沖靜態(tài)RAM)
MT58L128L18P 128K x 18, Pipelined, SCD SyncBurst SRAM(2Mb,流水線式,單循環(huán)取消選擇,同步脈沖靜態(tài)存儲器)
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