參數(shù)資料
型號(hào): MT55L256V18P1
廠商: Micron Technology, Inc.
英文描述: 2.5V I/O,256K x 18,Flow-Through ZBT SRAM(2.5V輸入/輸出,4Mb流通式同步靜態(tài)存儲(chǔ)器)
中文描述: 2.5VI /輸出,256 × 18,流量通過(guò)ZBT SRAM的電壓(2.5V輸入/輸出,4Mb的流通式同步靜態(tài)存儲(chǔ)器)
文件頁(yè)數(shù): 19/25頁(yè)
文件大小: 434K
代理商: MT55L256V18P1
19
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_2.p65
Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
PRELIMINARY
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
Q
50
V = 1.5V
Z = 50
Figure 1
Q
351
317
5pF
+3.3V
Figure 2
3.3V I/O AC TEST CONDITIONS
Input pulse levels ...................................V
SS
to 3.3V
Input rise and fall times..................................... 1ns
Input timing reference levels .......................... 1.5V
Output reference levels ................................... 1.5V
Output load ............................. See Figures 1 and 2
LOAD DERATING CURVES
The Micron 256K x 18, 128K x 32, and 128K x 36 ZBT
SRAM timing is dependent upon the capacitive loading
on the outputs.
Consult the factory for copies of I/O current versus
voltage curves.
Q
50
V = 1.25V
Z = 50
Figure 3
Q
225
225
5pF
+2.5V
Figure 4
2.5V I/O AC TEST CONDITIONS
Input pulse levels ...................................V
SS
to 2.5V
Input rise and fall times..................................... 1ns
Input timing reference levels ........................ 1.25V
Output reference levels ................................. 1.25V
Output load ............................. See Figures 3 and 4
3.3V I/O Output Load Equivalents
2.5V I/O Output Load Equivalents
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