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參數(shù)資料
| 型號(hào)： | MT54W4MH8BF-5 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 36Mb QDR⑩II SRAM 2-WORD BURST |
| 中文描述： | ⑩分配36MB四年防務(wù)審查II SRAM的2字爆 |
| 文件頁數(shù)： | 24/27頁 |
| 文件大?。?/td> | 302K |
| 代理商： | MT54W4MH8BF-5 |
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4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V V
DD
, HSTL, QDRIIb2 SRAM
ADVANCE
36Mb: 1.8V V
DD
, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
24
2002, Micron Technology Inc.
IDENTIFICATION REGISTER DEFINITIONS
INSTRUCTION FIELD
REVISION NUMBER (31:28)
DEVICE ID (28:12)
ALL DEVICES
000
00def0Wx0t0q0b0s0 def = 001 for 36Mb density
wx = 11 for x36, 10 for x18, 00 for x9, and 01 for x8
t = 1 for DLL version, 0 for non-DLL version
q = 1 for QDR, 0 for DDR
b = 1 for four-word burst, 0 for two-word burst
s = 1 for separate I/O, 0 for common I/O
00000101100
Allows unique identification of SRAM vendor.
DESCRIPTION
Version number.
MICRON JEDEC ID CODE
(11:1)
ID Register Presence
Indicator (0)
1
Indicates the presence of an ID register.
SCAN REGISTER SIZES
REGISTER NAME
BIT SIZE (x18)
3
1
32
109
Instruction
Bypass
ID
Boundary Scan
INSTRUCTION CODES
INSTRUCTION
CODE
000
DESCRIPTION
Captures I/O ring contents. Places the boundary scan register between
TDI and TDO.
Loads the ID register with the vendor ID code and places the register
between TDI and TDO. This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between
TDI and TDO. Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between
TDI and TDO.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does
not affect SRAM operations.
EXTEST
1,
2
IDCODE
001
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
RESERVED
RESERVED
BYPASS
101
110
111
NOTE:
1. Data in output register is not guaranteed if EXTEST instruction is loaded.
2. After performing EXTEST, power-up conditions are required in order to return part to normal operation.
相關(guān)PDF資料 |
PDF描述 |
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| MT54W4MH8BF-6 | 36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH8BF-7.5 | 36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9B | 36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9B-4 | 36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9B-5 | 36Mb QDR⑩II SRAM 2-WORD BURST |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT54W4MH8BF-6 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH8BF-7.5 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9B | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9B-4 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:36Mb QDR⑩II SRAM 2-WORD BURST |
| MT54W4MH9B-5 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:36Mb QDR⑩II SRAM 2-WORD BURST |
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