參數(shù)資料
型號(hào)： MT48LC8M16A2TG-8EIT
廠(chǎng)商： Micron Technology, Inc.
英文描述： SYNCHRONOUS DRAM
中文描述： 同步DRAM
文件頁(yè)數(shù)： 36/59頁(yè)
文件大小： 1822K
代理商： MT48LC8M16A2TG-8EIT
36
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
128Mb: x4, x8, x16
SDRAM
15. Timing actually specified by
t
WR plus
t
RP; clock(s)
specified as a reference only at minimum cycle rate.
16. Timing actually specified by
t
WR.
17. Required clocks are specified by JEDEC functionality
and are not dependent on any timing parameter.
18. The I
DD
current will increase or decrease propor-
tionally according to the amount of frequency alter-
ation for the test condition.
19. Address transitions average one transition every two
clocks.
20. CLK must be toggled a minimum of two times during
this period.
21. Based on
t
CK = 10ns for -8E and
t
CK = 7.5ns for -75 and
-7E .
22. V
IH
overshoot: V
IH
(MAX) = V
DD
Q + 2V for a pulse width
≤
3ns, and the pulse width cannot be greater than one
third of the cycle rate. V
IL
undershoot: V
IL
(MIN) = -2V
for a pulse width
≤
3ns.
23. The clock frequency must remain constant (stable
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during access
or precharge states (READ, WRITE, including
t
WR,
and PRECHARGE commands). CKE may be used to
reduce the data rate.
24. Auto precharge mode only. The precharge timing
budget (
t
RP) begins 7ns for -7E, 7.5ns for -75, and 7ns
for -8E after the first clock delay, after the last WRITE
is executed. May not exceed limit set for precharge
mode.
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27.
t
AC for -75/-7E at CL = 3 with no load is 4.6ns and is
guaranteed by design.
28. Parameter guaranteed by design.
29. PC100 specifies a maximum of 4pF.
30. PC100 specifies a maximum of 5pF.
31. PC100 specifies a maximum of 6.5pF.
32. For -8E, CL = 2 and
t
CK = 10ns; for -75, CL = 3 and
t
CK = 7.5ns; for -7E, CL = 2 and
t
CK = 7.5ns.
33. CKE is HIGH during refresh command period
t
RFC (MIN) else CKE is LOW. The I
DD
6 limit is actu-
ally a nominal value and does not result in a fail
value.
34. PC133 specifies a minimum of 2.5pF.
35. PC133 specifies a minimum of 2.5pF.
36. PC133 specifies a minimum of 3.0pF.
NOTES
1.
All voltages referenced to V
SS
.
2.
This parameter is sampled. V
DD
, V
DD
Q = +3.3V;
f = 1 MHz, T
A
= 25°C; pin under test biased at 1.4V.
3.
I
DD
is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
4.
Enables on-chip refresh and address counters.
5.
The minimum specifications are used only to
indicate cycle time at which proper operation over
the full temperature range (0°C
≤
T
A
≤
+70°C and -
40°C
≤
T
A
≤
+85°C for IT parts) is ensured.
6.
An initial pause of 100μs is required after power-up,
followed by two AUTO REFRESH commands, before
proper device operation is ensured. (V
DD
and V
DD
Q
must be powered up simultaneously. V
SS
and V
SS
Q
must be at same potential.) The two AUTO REFRESH
command wake-ups should be repeated any time
the
t
REF refresh requirement is exceeded.
7.
AC characteristics assume
t
T = 1ns.
8.
In addition to meeting the transition rate specifica-
tion, the clock and CKE must transit between V
IH
and
V
IL
(or between V
IL
and V
IH
) in a monotonic manner.
9.
Outputs measured at 1.5V with equivalent load:
Q
50pF
10.
t
HZ defines the time at which the output achieves the
open circuit condition; it is not a reference to V
OH
or
V
OL
. The last valid data element will meet
t
OH before
going High-Z.
11. AC timing and I
DD
tests have V
IL
= 0V and V
IH
= 3V, with
timing referenced to 1.5V crossover point. If the in-
put transition time is longer than 1 ns, then the
timing is referenced at V
IL
(MAX) and V
IH
(MIN) and
no longer at the 1.5V crossover point. Refer to Micron
Technical Note TN-48-09 for more details.
12. Other input signals are allowed to transition no more
than once every two clocks and are otherwise at valid
V
IH
or V
IL
levels.
13. I
DD
specifications are tested after the device is prop-
erly initialized.
14. Timing actually specified by
t
CKS; clock(s) specified
as a reference only at minimum cycle rate.
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