參數(shù)資料
型號(hào)： MT48LC8M16A2TG-8EIT
廠商： Micron Technology, Inc.
英文描述： SYNCHRONOUS DRAM
中文描述： 同步DRAM
文件頁(yè)數(shù)： 24/59頁(yè)
文件大?。?/td> 1822K
代理商： MT48LC8M16A2TG-8EIT
24
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65
–
Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
128Mb: x4, x8, x16
SDRAM
Fixed-length or full-page WRITE bursts can be trun-
cated with the BURST TERMINATE command. When
truncating a WRITE burst, the input data applied coinci-
dent with the BURST TERMINATE command will be
ignored. The last data written (provided that DQM is
LOW at that time) will be the input data applied one clock
previous to the BURST TERMINATE command. This is
shown in Figure 19, where data
n
is the last desired data
element of a longer burst.
Figure 21
Power-Down
DON
’
T CARE
tRAS
tRC
tRCD
All banks idle
Input buffers gated off
Exit power-down mode.
(
)
(
)
(
)
(
)
(
)
(
)
tCKS
> tCKS
COMMAND
NOP
ACTIVE
Enter power-down mode.
NOP
CLK
CKE
(
)
(
)
(
)
(
)
Figure 20
PRECHARGE Command
Figure 19
Terminating a WRITE Burst
CS#
WE#
CAS#
RAS#
CKE
CLK
A10
HIGH
All Banks
Bank Selected
A0-A9
BA0,1
ABANK
CLK
DQ
T2
T1
T0
COMMAND
ADDRESS
BANK,
COL
n
WRITE
BURST
TERMINATE
NEXT
COMMAND
D
IN
n
(ADDRESS)
(DATA)
PRECHARGE
The PRECHARGE command (see Figure 20) is used to
deactivate the open row in a particular bank or the open
row in all banks. The bank(s) will be available for a subse-
quent row access some specified time (
t
RP) after the
PRECHARGE command is issued. Input A10 determines
whether one or all banks are to be precharged, and in the
case where only one bank is to be precharged, inputs
BA0, BA1 select the bank. When all banks are to be
precharged, inputs BA0, BA1 are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state
and must be activated prior to any READ or WRITE com-
mands being issued to that bank.
POWER-DOWN
Power-down occurs if CKE is registered LOW coinci-
dent with a NOP or COMMAND INHIBIT when no ac-
cesses are in progress. If power-down occurs when all
banks are idle, this mode is referred to as precharge
power-down; if power-down occurs when there is a row
active in any bank, this mode is referred to as active
power-down. Entering power-down deactivates the in-
put and output buffers, excluding CKE, for maximum
power savings while in standby. The device may not
remain in the power-down state longer than the refresh
period (64ms) since no refresh operations are performed
in this mode.
The power-down state is exited by registering a NOP
or COMMAND INHIBIT and CKE HIGH at the desired
clock edge (meeting
t
CKS). See Figure 21.
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