參數(shù)資料
型號(hào)： MT48LC8M16A2TG-8E
廠商： Micron Technology, Inc.
英文描述： SYNCHRONOUS DRAM
中文描述： 同步DRAM
文件頁數(shù)： 20/59頁
文件大小： 1822K
代理商： MT48LC8M16A2TG-8E
20
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65
–
Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
128Mb: x4, x8, x16
SDRAM
Figure 11
READ to PRECHARGE
A fixed-length READ burst may be followed by, or
truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not activated),
and a full-page burst may be truncated with a
PRECHARGE command to the same bank. The
PRECHARGE command should be issued
x
cycles before
the clock edge at which the last desired data element is
valid, where
x
equals the CAS latency minus one. This is
shown in Figure 11 for each possible CAS latency; data
element
n
+ 3 is either the last of a burst of four or the last
desired of a longer burst. Following the PRECHARGE
command, a subsequent command to the same bank
cannot be issued until
t
RP is met. Note that part of the row
precharge time is hidden during the access of the last
data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the opti-
mum time (as described above) provides the same op-
eration that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
DON
’
T CARE
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
NOP
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
PRECHARGE
ACTIVE
tRP
T7
NOTE:
DQM is LOW.
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
NOP
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
PRECHARGE
ACTIVE
tRP
T7
X
= 1 cycle
CAS Latency = 2
CAS Latency = 3
X
= 2 cycles
BANK
a
,
COL
n
BANK
a
,
ROW
BANK
(
a
or all)
BANK
a
,
COL
n
BANK
a
,
ROW
BANK
(
a
or all)
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