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參數(shù)資料
| 型號(hào)： | MT48LC8M16A2TG-8E |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件頁數(shù)： | 16/59頁 |
| 文件大?。?/td> | 1822K |
| 代理商： | MT48LC8M16A2TG-8E |
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16
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65
–
Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
128Mb: x4, x8, x16
SDRAM
Upon completion of a burst, assuming no other com-
mands have been initiated, the DQs will go High-Z. A full-
page burst will continue until terminated. (At the end of
the page, it will wrap to column 0 and continue.)
Data from any READ burst may be truncated with a
subsequent READ command, and data from a fixed-length
READ burst may be immediately followed by data from a
READ command. In either case, a continuous flow of data
can be maintained. The first data element from the new
burst follows either the last element of a completed burst
or the last desired data element of a longer burst that is
being truncated. The new READ command should be
issued
x
cycles before the clock edge at which the last
desired data element is valid, where
x
equals the CAS
latency minus one.
READs
READ bursts are initiated with a READ command, as
shown in Figure 5.
The starting column and bank addresses are provided
with the READ command, and auto precharge is either
enabled or disabled for that burst access. If auto precharge
is enabled, the row being accessed is precharged at the
completion of the burst. For the generic READ com-
mands used in the following illustrations, auto precharge
is disabled.
During READ bursts, the valid data-out element from
the starting column address will be available following
the CAS latency after the READ command. Each subse-
quent data-out element will be valid by the next positive
clock edge. Figure 6 shows general timing for each pos-
sible CAS latency setting.
Figure 5
READ Command
Figure 6
CAS Latency
CLK
DQ
T2
T1
T3
T0
CAS Latency = 3
LZ
t
D
OUT
tOH
COMMAND
NOP
READ
tAC
NOP
T4
NOP
DON’T CARE
UNDEFINED
CLK
DQ
T2
T1
T3
T0
CAS Latency = 2
LZ
t
D
OUT
tOH
COMMAND
NOP
READ
tAC
NOP
CS#
WE#
CAS#
RAS#
CKE
CLK
COLUMN
ADDRESS
A10
BA0,1
HIGH
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK
ADDRESS
A0-A9, A11: x4
A0-A9: x8
A0-A8: x16
A11: x8
A9, A11: x16
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