參數(shù)資料
型號： MT48LC8M16A2TG-75
廠商： Micron Technology, Inc.
英文描述： SYNCHRONOUS DRAM
中文描述： 同步DRAM
文件頁數(shù)： 21/59頁
文件大?。?/td> 1822K
代理商： MT48LC8M16A2TG-75
21
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65
–
Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
128Mb: x4, x8, x16
SDRAM
Figure 12
Terminating a READ Burst
PRECHARGE command is that it requires that the com-
mand and address buses be available at the appropriate
time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate
fixed-length or full-page bursts.
Full-page READ bursts can be truncated with the
BURST TERMINATE command, and fixed-length READ
bursts may be truncated with a BURST TERMINATE com-
mand, provided that auto precharge was not activated.
The BURST TERMINATE command should be issued
x
cycles before the clock edge at which the last desired data
element is valid, where
x
equals the CAS latency minus
one. This is shown in Figure 12 for each possible CAS
latency; data element
n
+ 3 is the last desired data ele-
ment of a longer burst.
DON
’
T CARE
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
BANK,
COL
n
NOP
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
BURST
TERMINATE
NOP
T7
NOTE:
DQM is LOW.
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
BANK,
COL
n
NOP
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
BURST
TERMINATE
NOP
X
= 1 cycle
CAS Latency = 2
CAS Latency = 3
X
= 2 cycles
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