參數(shù)資料
型號: MT48LC64M4A2
廠商: Micron Technology, Inc.
英文描述: SYNCHRONOUS DRAM
中文描述: 同步DRAM
文件頁數(shù): 47/62頁
文件大?。?/td> 1517K
代理商: MT48LC64M4A2
47
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65
Rev. E; Pub. 3/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
256Mb: x4, x8, x16
SDRAM
SINGLE READ – WITHOUT AUTO PRECHARGE
1
TIMING PARAMETERS
-7E
-75
SYMBOL*
t
AC (3)
t
AC (2)
t
AH
t
AS
t
CH
t
CL
t
CK (3)
t
CK (2)
t
CKH
t
CKS
MIN
MAX
5.4
5.4
MIN
MAX
5.4
6
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.8
1.5
2.5
2.5
7
7.5
0.8
1.5
0.8
1.5
2.5
2.5
7.5
10
0.8
1.5
t
CMH
t
CMS
t
HZ (3)
t
HZ (2)
t
LZ
t
OH
t
RAS
t
RC
t
RCD
t
RP
0.8
1.5
0.8
1.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.4
5.4
5.4
6
1
3
37
60
15
15
1
3
44
66
20
20
120,000
120,000
*CAS latency indicated in parentheses.
-7E
-75
SYMBOL*
MIN
MAX
MIN
MAX
UNITS
NOTE:
1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a
manual
PRECHARGE.
2. x16: A9, A11, and A12 =
Don
t Care
x8: A11 and A12 =
Don
t Care
x4: A12 =
Don
t Care
3. PRECHARGE command not allowed else
t
RAS would be violated.
ALL BANKS
tCH
tCL
tCK
tAC
tLZ
tRP
tRAS
tRC
tRCD
CAS Latency
tOH
D
OUT
m
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
ROW
ROW
BANK
BANK(S)
BANK
ROW
ROW
BANK
tHZ
tCMH
tCMS
NOP
NOP
NOP
PRECHARGE
ACTIVE
NOP
READ
ACTIVE
NOP
DISABLE AUTO PRECHARGE
SINGLE BANKS
DON
T CARE
UNDEFINED
COLUMN
m
2
tCKH
tCKS
T0
T1
T2
T3
T4
T5
T6
T7
T8
DQM /
DQML, DQMU
CKE
CLK
A0-A9, A11,A12
DQ
BA0, BA1
A10
COMMAND
3
3
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