參數(shù)資料
型號(hào)： MT48LC4M32TG-10
元件分類(lèi)： DRAM
英文描述： 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54
封裝： 0.400 INCH, PLASTIC, TSOP2-54
文件頁(yè)數(shù)： 56/69頁(yè)
文件大?。?/td> 6213K
代理商： MT48LC4M32TG-10
128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
6
2001 Micron Technology, Inc. All rights reserved.
Figure 4: 128Mb SDRAM Part Numbers
NOTE:
Not all speeds and configurations are avail-
able.
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged compo-
nents have an abbreviated part marking that is differ-
ent from the part number. Micron's new FBGA Part
Marking Decoder makes it easier to understand that
part marking. Visit the web site at www.micron.com/
General Description
The Micron 128Mb SDRAM is a high-speed
CMOS, dynamic random-access memory containing
134,217,728 bits. It is internally configured as a quad-
bank DRAM with a synchronous interface (all signals
are registered on the positive edge of the clock signal,
CLK). Each of the x16’s 33,554,432-bit banks is orga-
nized as 4,096 rows by 512 columns by 16 bits. Each of
the x32’s 33,554,432-bit banks is organized as 4,096
rows by 256 columns by 32 bits.
Read and write accesses to the SDRAM are burst ori-
ented; accesses start at a selected location and con-
tinue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed
(BA0, BA1 select the bank; A0-A11) select the row). The
address bits registered coincident with the READ or
WRITE command are used to select the starting col-
umn location for the burst access.
The SDRAM provides for programmable read or
write burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence.
The 128Mb SDRAM uses an internal pipelined
architecture to achieve high-speed operation. This
architecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one bank
while accessing one of the other three banks will hide
the precharge cycles and provide seamless high-speed,
random-access operation.
The 128Mb SDRAM is designed to operate in 3.3V or
2.5V low-power memory systems. The 2.5V version is
compatible with 1.8V I/O interface. An auto refresh
-
Configuration
MT48
Package
Speed
Temperature
Configuration
8 Meg x 16
4 Meg x 32
8M16
4M32
Package
54-ball FBGA (8x8mm)
54-ball FBGA (8x8mm) Lead-Free
90-ball VFBGA (8x13mm)
90-ball VFBGA (8x13mm ) Lead-Free
54-Pin TSOP II (400 Mil)
54-Pin TSOP II (400 Mil) Lead-Free
IT
XT
Operating Temp
Standard
Industrial Temp
Extended Temp
Example Part Number: MT48V4M32LFF5-10XT
Voltage (VDD/VDDQ)
3.3V/ 3.3V
2.5V / 2.5V - 1.8V
LC
V
VDD/
VDDQ
LF
Speed Grade
tCK=7.5ns, CL = 3
tCK=8ns, CL = 3
tCK=10ns, CL = 3
-75M
-8
-10
F4
B4
F5
B5
TG
P
相關(guān)PDF資料
PDF描述
MT48V8M16LFB4-8XT 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54
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