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參數(shù)資料
| 型號： | MT48LC4M32TG-10 |
| 元件分類： | DRAM |
| 英文描述： | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 48/69頁 |
| 文件大?。?/td> | 6213K |
| 代理商： | MT48LC4M32TG-10 |
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128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
52
2001 Micron Technology, Inc. All rights reserved.
Figure 39: Self Refresh Mode
NOTE:
1. No maximum time limit for Self Refresh. tRAS (MAX) only applies to non-Self Refresh mode.
2. tXSR requires a minimum of two clocks regardless of frequency or timing.
3. As a general rule, any time Self Refresh is exited, the DRAM may not re-enter the Self Refresh Mode until all rows have
been refreshed via the Auto Refresh command at the distributed refresh rate, ( tREF / number of rows), or faster. How-
ever, the following exception is allowed. Self Refresh Mode may be re-entered any time after exiting, if the following
conditions are all met:
a.) The DRAM has been in the Self Refresh Mode for a minimum of 64ms prior to exiting.
b.) tXSR has not been violated.
c.) At least two Auto Refresh commands are performed during each 15.625us interval while the DRAM remains out
of the Self Refresh mode.
DON’T CARE
tCH
tCL
tCK
tRP
CKE
CLK
DQ
Enter self refresh mode
Precharge all
active banks
tXSR2
CLK stable prior to exiting
self refresh mode
Exit self refresh mode
(Restart refresh time base)
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COMMAND
tCMH
tCMS
AUTO
REFRESH
PRECHARGE
NOP
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BA0, BA1
BANK(S)
High-Z
tCKS
AH
AS
AUTO
REFRESH
> tRAS1
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tCKH
tCKS
DQMU, DQML
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t
A0-A9, A11
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ALL BANKS
SINGLE BANK
A10
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T0
T1
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Tn + 1
To + 1
To + 2
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