- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384755 > MT48LC32M16A2 (Micron Technology, Inc.) SYNCHRONOUS DRAM PDF資料下載
參數(shù)資料
| 型號： | MT48LC32M16A2 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件頁數(shù)： | 11/55頁 |
| 文件大?。?/td> | 1828K |
| 代理商： | MT48LC32M16A2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁
11
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65
–
Rev. D; Pub 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
512Mb: x4, x8, x16
SDRAM
ADVANCE
TRUTH TABLE 1 – COMMANDS AND DQM OPERATION
(Note: 1)
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
CS# RAS# CAS# WE# DQM
H
X
X
L
H
H
L
L
H
L
H
L
L
H
L
L
H
H
L
L
H
L
L
L
ADDR
X
X
Bank/Row
Bank/Col
Bank/Col
X
Code
X
DQs
X
X
X
X
Valid
Active
X
X
NOTES
X
H
H
H
L
L
L
H
X
X
X
3
4
4
L/H
8
L/H
8
X
X
X
5
6, 7
L
–
–
L
–
–
L
–
–
L
–
–
X
L
H
Op-Code
–
–
X
2
8
8
Active
High-Z
following the Operation section; these tables provide
current state/next state information.
COMMANDS
Truth Table 1 provides a quick reference of available
commands. This is followed by a written description of
each command. Three additional Truth Tables appear
NOTE:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-A11 define the op-code written to the Mode Register, and A12 should be driven LOW.
3. A0-A12 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A9, A11, A12 (x4); A0-A9, A11 (x8); or A0-A9 (x16) provide column address; A10 HIGH enables the auto precharge
feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being
read from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are
“
Don
’
t
Care.
”
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are
“
Don
’
t Care
”
except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
相關PDF資料 |
PDF描述 |
|---|---|
| MT48LC8M16A2FB-75LIT | SYNCHRONOUS DRAM |
| MT48LC8M16A2FB-7E | SYNCHRONOUS DRAM |
| MT48LC8M16A2FB-7EIT | SYNCHRONOUS DRAM |
| MT48LC8M16A2FB-7EL | SYNCHRONOUS DRAM |
| MT48LC8M16A2FB-7ELIT | SYNCHRONOUS DRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT48LC32M16A2-75ITC | 制造商:Micron Technology Inc 功能描述: |
| MT48LC32M16A2P-75 | 制造商:Micron Technology Inc 功能描述: |
| MT48LC32M16A2P-75 C TR | 制造商:Micron Technology Inc 功能描述:DRAM Chip SDRAM 512M-Bit 32Mx16 3.3V 54-Pin TSOP-II T/R 制造商:Micron Technology 功能描述:DRAM Chip SDRAM 512M-Bit 32Mx16 3.3V 54-Pin TSOP-II T/R |
發(fā)布緊急采購，3分鐘左右您將得到回復。