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參數(shù)資料
| 型號： | MT312T-Y |
| 廠商： | Marktech Optoelectronics |
| 英文描述： | 2x4mm Rectangular LED Lamps |
| 中文描述： | 2x4mm矩形發(fā)光二極管 |
| 文件頁數(shù)： | 81/90頁 |
| 文件大?。?/td> | 318K |
| 代理商： | MT312T-Y |
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Electrical Characteristics
MT312
81
Note 1.8V tolerant pins with thresholds related to 3.3V.
Pin
Name
Description
I/O
Note
V
mA
53
CLK1
2-wire serial bus clock
I
CMOS
5
1
5
1
54
DATA1
2-wire serial bus data
I/O
Open
drain
6
57
IRQ
Active low interrupt output. A low output
on this pin indicates an event has
occurred and the microprocessor should
read the interrupt registers. Reading all
interrupt registers resets this pin.
O
Open
drain
5
1
6
58
MOCLK
MPEG clock output at the data byte rate.
O
CMOS
Tri-
state
3.3
1
69,68,66,65,
64,63,61,59
MDO[7:0]
MPEG transport packet data output bus.
O
CMOS
Tri-
state
3.3
1
71
MDOEN
Logic 1 = MPEG data and clock outputs
disable - Tri-state. Logic 0 = MPEG data
and clock outputs enable
I
CMOS
5
1
72
MOVAL
MPEG data output valid. This pin is high
during the MOCLK clock cycles when
valid data bytes are being output.
O
CMOS
Tri-
state
3.3
1
75
BKERR
Active low uncorrectable block indicator
OR no signal indicator selected by ERR
IND bit 7 of MON CTRL register.
O
CMOS
Tri-
state
3.3
1
76
MOSTRT
MPEG output start signal, high on the
fi
rst byte of a packet.
O
CMOS
Tri-
state
3.3
1
2,9,17,42,50,
55,62,67
CVDD
Core Digital CVDD. All pins must be
connected.
1.8
13,73
VDD
Peripheral VDD. All pins must be
connected.
3.3
37
ADCAVDD
ADC core analogue VDD. All pins must
be connected.
1.8
30
ADCDVDD
ADC core digital VDD. All pins must be
connected.
3.3
25
ADCFVDD
ADC core front end VDD. All pins must
be connected.
3.3
21
PLLVDD
PLL VDD. All pins must be connected.
1.8
1,10,20,41,51,
60,70
CVSS
Digital VSS. All pins must be connected.
0
15,56,74
VSS
Peripheral VSS. All pins must be
connected.
0
36
ADCAGND
ADC core analogue VSS. Must be
connected to analogue GND.
0
31
ADCDGND
ADC core digital VSS. Must be
connected to analogue GND.
0
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